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19-2745; Rev 1; 9/03
KIT ATION EVALU ABLE AVAIL
Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies
General Description Features
o Dual-Phase, Quick-PWM Controller o 0.75% VOUT Accuracy Over Line, Load, and Temperature (1.3V) o Active Voltage Positioning with Adjustable Gain and Offset o 5-Bit On-Board DAC: 0.675V to 1.55V Output Adjust Range o Selectable 100kHz/200kHz/300kHz/550kHz Switching Frequency o 4V to 28V Battery Input Voltage Range o Adjustable Slew-Rate Control o Drives Large Synchronous Rectifier MOSFETs o Selectable Output Overvoltage Protection o Undervoltage and Thermal-Fault Protection o Power Sequencing and Timing o Selectable Suspend Voltage o Soft-Shutdown o Selectable Single- or Dual-Phase Pulse Skipping
MAX1544
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The MAX1544 is a dual-phase, Quick-PWMTM, stepdown controller for AMD HammerTM CPU core supplies. Dual-phase operation reduces input ripple current requirements and output voltage ripple while easing component selection and layout difficulties. The QuickPWM control scheme provides instantaneous response to fast load-current steps. The MAX1544 includes active voltage positioning with adjustable gain and offset, reducing power dissipation and bulk output capacitance requirements. The MAX1544 is intended for two different notebook CPU core applications: stepping down the battery directly or stepping down the 5V system supply to create the core voltage. The single-stage conversion method allows this device to directly step down high-voltage batteries for the highest possible efficiency. Alternatively, two-stage conversion (stepping down the 5V system supply instead of the battery) at a higher switching frequency provides the minimum possible physical size. The MAX1544 complies with AMD's desktop and mobile CPU specifications. The switching regulator features soft-start and power-up sequencing, and soft-shutdown. The MAX1544 also features independent four-level logic inputs for setting the suspend voltage (S0-S1). The MAX1544 includes output undervoltage protection, thermal protection, and voltage regulator power-OK (VROK) output. When any of these protection features detect a fault, the controller shuts down. Additionally, the MAX1544 includes selectable overvoltage protection. The MAX1544 is available in a low-profile, 40-pin 6mm x 6mm thin QFN package. For other CPU platforms, refer to the pin-to-pin compatible MAX1519/MAX1545 and MAX1532/MAX1546/MAX1547 data sheets.
Ordering Information
PART MAX1544ETL TEMP RANGE -40C to +100C PIN-PACKAGE 40 Thin QFN 6mm 6mm
Pin Configuration
V+ BSTS CSN CMN CMP LXS DHS DLS CSP TOP VIEW PGND
Applications
AMD Hammer Desktop or Notebook PCs Multiphase CPU Core Supply Voltage-Positioned Step-Down Converters Servers/Desktop Computers
TIME TON SUS S0 S1 SHDN OFS REF ILIM VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
30 29 28 27 26 25 24 23 22 21
MAX1544
VDD DLM DHM LXM BSTM VROK D0 D1 D2 D3
CCI FB OAINOAIN+
CCV GNDS
SKIP
Quick-PWM is a trademark of Maxim Integrated Products, Inc. Hammer is a trademark of AMD.
GND
THIN QFN 1
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
OVP D4
Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies MAX1544
ABSOLUTE MAXIMUM RATINGS
V+ to GND ..............................................................-0.3V to +30V VCC to GND ..............................................................-0.3V to +6V VDD to PGND............................................................-0.3V to +6V SKIP, SUS, D0-D4 to GND.......................................-0.3V to +6V ILIM, FB, OFS, CCV, CCI, REF, OAIN+, OAIN- to GND.........................................-0.3V to (VCC + 0.3V) CMP, CSP, CMN, CSN, GNDS to GND ......-0.3V to (VCC + 0.3V) TON, TIME, VROK, S0-S1, OVP to GND ....-0.3V to (VCC + 0.3V) SHDN to GND (Note 1)...........................................-0.3V to +18V DLM, DLS to PGND ....................................-0.3V to (VDD + 0.3V) BSTM, BSTS to GND ..............................................-0.3V to +36V DHM to LXM ...........................................-0.3V to (VBSTM + 0.3V) LXM to BSTM............................................................-6V to +0.3V DHS to LXS..............................................-0.3V to (VBSTS + 0.3V) LXS to BSTS .............................................................-6V to +0.3V GND to PGND .......................................................-0.3V to +0.3V REF Short-Circuit Duration .........................................Continuous Continuous Power Dissipation (TA = +70C) 40-Pin 6mm 6mm Thin QFN (derate 23.2mW/C above +70C) ...............................1.860W Operating Temperature Range .........................-40C to +100C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Note 1: SHDN may be forced to 12V for the purpose of debugging prototype boards using the no-fault test mode, which disables fault protection and overlapping operation.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V+ = 15V, VCC = VDD = V SHDN = VTON = V SKIP = VS0 = VS1 = VOVP = 5V, VFB = VCMP = VCMN = VCSP = VCSN = 1.3V, OFS = SUS = GNDS = D0-D4 = GND; TA = 0C to +85C, unless otherwise specified. Typical values are at TA = +25C.)
PARAMETER PWM CONTROLLER Input Voltage Range DC Output Voltage Accuracy (Note 2) Line Regulation Error Input Bias Current OFS Input Range VOUT/VOFS; VOFS = VOFS, VOFS = 0 to 1V VOUT/VOFS; VOFS = VOFS-VREF, VOFS = 1V to 2V VOUT/VGNDS 1000kHz nominal, RTIME = 15k TIME Frequency Accuracy fTIME 500kHz nominal, RTIME = 30k 250kHz nominal, RTIME = 60k Shutdown, RTIME = 30k IFB, IGNDS IOFS Battery voltage, V+ VCC, VDD V+ = 4.5V to 28V, includes load regulation error DAC codes 1V DAC codes from 0.60V to 1V 4 4.5 -10 -15 5 -2 -0.1 0 -0.129 -0.129 -20 AGNDS 0.97 900 460 225 0.99 1000 500 250 125 -0.125 -0.125 +2 +0.1 2 -0.117 V/V -0.117 +200 1.01 1100 540 275 kHz mV V/V 28 5.5 +10 +15 mV mV A V V SYMBOL CONDITIONS MIN TYP MAX UNITS
VCC = 4.5V to 5.5V, V+ = 4.5V to 28V FB, GNDS OFS
OFS Gain
AOFS
GNDS Input Range GNDS Gain
2
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Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, VCC = VDD = V SHDN = VTON = V SKIP = VS0 = VS1 = VOVP = 5V, VFB = VCMP = VCMN = VCSP = VCSN = 1.3V, OFS = SUS = GNDS = D0-D4 = GND; TA = 0C to +85C, unless otherwise specified. Typical values are at TA = +25C.)
PARAMETER SYMBOL CONDITIONS TON = GND (550kHz) TON = REF (300kHz) TON = open (200kHz) TON = VCC (100kHz) Minimum Off-Time (Note 3) BIAS AND REFERENCE Quiescent Supply Current (VCC) Quiescent Supply Current (VDD) Quiescent Battery Supply Current (V+) Shutdown Supply Current (VCC) Shutdown Supply Current (VDD) Shutdown Battery Supply Current (V+) Reference Voltage Reference Load Regulation FAULT PROTECTION Output Overvoltage Protection Threshold VOVP SKIP = VCC, measured at FB with respect to unloaded output voltage SKIP = REF or GND tOVP FB forced 2% above trip threshold Measured at FB with respect to unloaded output voltage FB forced 2% below trip threshold Lower threshold (undervoltage) Upper threshold (overvoltage) SKIP = VCC -12 13 16 2.00 10 19 % V s VREF VREF ICC IDD IV+ Measured at VCC, FB forced above the regulation point, OAIN- = FB, VOAIN+ = 1.3V Measured at VDD, FB forced above the regulation point Measured at V+ Measured at VCC, SHDN = GND Measured at VDD, SHDN = GND Measured at V+, SHDN = GND, VCC = VDD = 0 or 5V VCC = 4.5V to 5.5V, IREF = 0 IREF = -10A to 100A 1.990 -10 1.70 <1 25 4 <1 <1 2.000 3.20 5 40 10 5 5 2.010 +10 mA A A A A A V mV tOFF(MIN) TON = GND TON = VCC, open, or REF MIN 155 320 475 920 TYP 180 355 525 1000 300 400 MAX 205 390 ns 575 1140 375 480 ns UNITS
MAX1544
On-Time (Note 3)
tON
V+ = 12V, VFB = VCCI = 1.2V
Output Overvoltage Propagation Delay Output Undervoltage Protection Threshold Output Undervoltage Propagation Delay
VUVP tUVP
67
70 10 -10
73
% s
VROK Threshold
Measured at FB with respect to unloaded output voltage
-8 %
+8
+10
+12
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3
Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies MAX1544
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, VCC = VDD = V SHDN = VTON = V SKIP = VS0 = VS1 = VOVP = 5V, VFB = VCMP = VCMN = VCSP = VCSN = 1.3V, OFS = SUS = GNDS = D0-D4 = GND; TA = 0C to +85C, unless otherwise specified. Typical values are at TA = +25C.)
PARAMETER Output Undervoltage Fault and VROK Transition Blanking Time (Note 4) VROK Startup Delay SYMBOL tBLANK CONDITIONS Measured from the time when FB reaches the voltage set by the DAC code; clock speed set by RTIME Measured from the time when FB first reaches the voltage set by the DAC code after startup tVROK FB forced 2% outside the VROK trip threshold ISINK = 3mA High state, VROK forced to 5.5V VUVLO(VCC) TSHDN Rising edge, hysteresis = 90mV, PWM disabled below this level Hysteresis = 10C 4.0 4.25 160 3 MIN TYP 24 MAX UNITS Clks
5
7
ms
VROK Delay VROK Output Low Voltage VROK Leakage Current VCC Undervoltage Lockout Threshold Thermal-Shutdown Threshold CURRENT LIMIT AND BALANCE Current-Limit Threshold Voltage (Positive, Default) Current-Limit Threshold Voltage (Positive, Adjustable) Current-Limit Threshold Voltage (Negative) Current-Limit Threshold Voltage (Zero Crossing) CMP, CMN, CSP, CSN Input Ranges CMP, CMN, CSP, CSN Input Current Secondary Driver-Disable Threshold ILIM Input Current Current-Limit Default Switchover Threshold Current-Balance Offset
10 0.4 1 4.4
s V A V C
VLIMIT VLIMIT VLIMIT(NEG) VZERO
CMP - CMN, CSP - CSN; ILIM = VCC CMP - CMN, CSP - CSN VILIM = 0.2V VILIM = 1.5V
28 8 73 -41
30 10 75 -36 1.5
32 12 77 -31
mV mV mV mV
CMP - CMN, CSP - CSN; ILIM = VCC, SKIP = VCC CMP - CMN, CSP - CSN; SKIP = GND
0 VCSP = VCSN = 0 to 5V VCSP IILIM VILIM (VCMP - VCMN) - (VCSP - VCSN); ICCI = 0, -20mV < (VCMP - VCMN) < 20mV, 1.0V < VCCI < 2.0V VILIM = 0 to 5V 3 -2 3 VCC - 1 0.1 VCC - 1
2 +2 VCC 0.4 200 VCC 0.4 +2
V A V nA V
VOS(IBAL)
-2
mV
4
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Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, VCC = VDD = V SHDN = VTON = V SKIP = VS0 = VS1 = VOVP = 5V, VFB = VCMP = VCMN = VCSP = VCSN = 1.3V, OFS = SUS = GNDS = D0-D4 = GND; TA = 0C to +85C, unless otherwise specified. Typical values are at TA = +25C.)
PARAMETER Current-Balance Transconductance GATE DRIVERS DH_ Gate-Driver On-Resistance DL_ Gate-Driver On-Resistance DH_ Gate-Driver Source/Sink Current DL_ Gate-Driver Sink Current DL_ Gate-Driver Source Current Dead Time VOLTAGE-POSITIONING AMPLIFIER Input Offset Voltage Input Bias Current Op Amp Disable Threshold Common-Mode Input Voltage Range Common-Mode Rejection Ratio Power-Supply Rejection Ratio Large-Signal Voltage Gain Output Voltage Swing Input Capacitance Gain-Bandwidth Product Slew Rate Capacitive-Load Stability LOGIC AND I/O SHDN Input High Voltage SHDN Input Low Voltage SHDN No-Fault Threshold OVP Input High Voltage OVP Input Low Voltage High Three-Level Input Logic Levels Logic Input Current D0-D4 Logic Input High Voltage SUS, SKIP SHDN, SKIP, SUS, OVP REF Low -1 1.6 2.7 1.2 2.3 0.8 +1 A V V VIH VIL V SHDN To enable no-fault mode 12 2.4 0.8 0.8 0.4 15 V V V V V No sustained oscillations VOS IBIAS VOAINVCM CMRR PSRR AOA Guaranteed by CMRR test VOAIN+ = VOAIN- = 0 to 2.5V VCC = 4.5V to 5.5V RL = 1k to VCC/2 |VOAIN+ - VOAIN-| 10mV, RL = 1k to VCC/2 VCC - VFBH VFBL OAIN+, OAIN3 0 70 75 80 115 100 112 77 47 11 3 0.3 400 300 200 -1 0.1 VCC - 1 +1 200 VCC 0.4 2.5 mV nA V V dB dB dB mV pF MHz V/s pF RON(DH) RON(DL) IDH IDL(SINK) BST_ - LX_ forced to 5V High state (pullup) Low start (pulldown) DH_ forced to 2.5V, BST_ - LX_ forced to 5V DL_ forced to 5V DL_ rising DH_ rising 1.0 1.0 0.4 1.6 4 1.6 35 26 4.5 4.5 2 A A A ns SYMBOL Gm(IBAL) CONDITIONS MIN TYP 400 MAX UNITS S
MAX1544
IDL(SOURCE) DL_ forced to 2.5V tDEAD
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5
Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies MAX1544
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, VCC = VDD = V SHDN = VTON = V SKIP = VS0 = VS1 = VOVP = 5V, VFB = VCMP = VCMN = VCSP = VCSN = 1.3V, OFS = SUS = GNDS = D0-D4 = GND; TA = 0C to +85C, unless otherwise specified. Typical values are at TA = +25C.)
PARAMETER D0-D4 Logic Input Low Voltage D0-D4 Input Current D0-D4 High Four-Level Input Logic Levels TON, S0-S1 Open REF Low Four-Level Input Current TON, S0-S1 forced to GND or VCC -3 -2 VCC 0.4 3.15 1.65 3.85 2.35 0.4 +3 A V SYMBOL CONDITIONS MIN TYP MAX 0.8 +2 UNITS V A
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V+ = 15V, VCC = VDD = V SHDN = VTON = V SKIP = VS0 = VS1 = VOVP = 5V, VFB = VCMP = VCMN = VCSP = VCSN = 1.3V, OFS = SUS = GNDS = D0-D4 = GND; TA = -40C to +100C, unless otherwise specified.) (Note 5)
PARAMETER PWM CONTROLLER Input Voltage Range DC Output Voltage Accuracy (Note 2) OFS Input Range VOUT/VOFS; VOFS = VOFS, VOFS = 0 to 1V VOUT/VOFS; VOFS = VOFS-VREF, VOFS = 1V to 2V VOUT/VGNDS 1000kHz nominal, RTIME = 15k TIME Frequency Accuracy fTIME 500kHz nominal, RTIME = 30k 250kHz nominal, RTIME = 60k TON = GND (550kHz) TON = REF (300kHz) TON = open (200kHz) TON = VCC (100kHz) Minimum Off-Time (Note 3) tOFF(MIN) TON = GND TON = VCC, open, or REF Battery voltage, V+ VCC, VDD V+ = 4.5V to 28V, includes load regulation error DAC codes 1V DAC codes from 0.60V to 1V 4 4.5 -13 -20 0 -0.131 -0.131 0.94 880 450 220 150 315 470 910 28 5.5 +13 +20 2 -0.115 V/V -0.115 1.01 1120 550 280 210 395 ns 580 1150 380 490 ns kHz V/V mV V V SYMBOL CONDITIONS MIN MAX UNITS
OFS GAIN
AOFS
GNDS Gain
AGNDS
On-Time (Note 3)
tON
V+ = 12V, VFB = VCCI = 1.2V
6
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Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, VCC = VDD = V SHDN = VTON = V SKIP = VS0 = VS1 = VOVP = 5V, VFB = VCMP = VCMN = VCSP = VCSN = 1.3V, OFS = SUS = GNDS = D0-D4 = GND; TA = -40C to +100C, unless otherwise specified.) (Note 5)
PARAMETER BIAS AND REFERENCE Quiescent Supply Current (VCC) Quiescent Supply Current (VDD) Quiescent Battery Supply Current (V+) Shutdown Supply Current (VCC) Shutdown Supply Current (VDD) Shutdown Battery Supply Current (V+) Reference Voltage FAULT PROTECTION Output Overvoltage Protection Threshold Output Undervoltage Protection Threshold VOVP VUVP SKIP = VCC, measured at FB with respect to unloaded output voltage Measured at FB with respect to unloaded output voltage Measured at FB with respect to unloaded output voltage Lower threshold (undervoltage) 13 67 -13 19 73 -7 % +7 +13 % % VREF ICC IDD IV+ Measured at VCC, FB forced above the regulation point, OAIN- = FB, VOAIN+ = 1.3V Measured at VDD, FB forced above the regulation point Measured at V+ Measured at VCC, SHDN = GND Measured at VDD, SHDN = GND Measured at V+, SHDN = GND, VCC = VDD = 0 or 5V VCC = 4.5V to 5.5V, IREF = 0 1.985 3.2 20 50 20 20 20 2.015 mA A A A A A V SYMBOL CONDITIONS MIN MAX UNITS
MAX1544
VROK Threshold
VROK Startup Delay
Upper threshold (overvoltage) SKIP = VCC Measured from the time when FB first reaches the voltage set by the DAC code after startup
3 3.90 4.45
ms V
VCC Undervoltage Lockout Rising edge, hysteresis = 90mV, PWM VUVLO(VCC) Threshold disabled below this level CURRENT LIMIT AND BALANCE Current-Limit Threshold Voltage (Positive, Default) Current-Limit Threshold Voltage (Positive, Adjustable) Current-Limit Threshold Voltage (Negative) Current-Balance Offset GATE DRIVERS DH_ Gate-Driver On-Resistance RON(DH) BST_ - LX_ forced to 5V VLIMIT VLIMIT VLIMIT(NEG) CMP - CMN, CSP - CSN; ILIM = VCC CMP - CMN, CSP - CSN VILIM = 0.2V VILIM = 1.5V
27 7 72 -30
33 13 78 -42
mV mV mV
CMP - CMN, CSP - CSN; ILIM = VCC, SKIP = VCC (VCMP - VCMN) - (VCSP - VCSN); ICCI = 0, -20mV < (VCMP - VCMN) < 20mV, 1.0V < VCCI < 2.0V
VOS(IBAL)
-3
+3
mV
4.5
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7
Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies MAX1544
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, VCC = VDD = V SHDN = VTON = V SKIP = VS0 = VS1 = VOVP = 5V, VFB = VCMP = VCMN = VCSP = VCSN = 1.3V, OFS = SUS = GNDS = D0-D4 = GND; TA = -40C to +100C, unless otherwise specified.) (Note 5)
PARAMETER DL_ Gate-Driver On-Resistance SYMBOL RON(DL) CONDITIONS High state (pullup) Low start (pulldown) -2.0 Guaranteed by CMRR test |VOAIN+ - VOAIN-| 10mV, RL = 1k to VCC/2 VIH VIL High Three-Level Input Logic Levels D0-D4 Logic Input High Voltage D0-D4 Logic Input Low Voltage OVP Input High Voltage OVP Input Low Voltage High Four-Level Input Logic Levels TON, S0-S1 Open REF Low VCC 0.4 3.15 1.65 3.85 2.35 0.4 V 2.4 0.8 SUS, SKIP REF Low 1.6 0.8 2.7 1.2 2.3 0.8 V V V V V VCC - VFBH VFBL 0.8 0.4 0 MIN MAX 4.5 2 +2.0 2.5 300 200 UNITS
VOLTAGE-POSITIONING AMPLIFIER Input Offset Voltage Common-Mode Input Voltage Range Output Voltage Swing LOGIC AND I/O SHDN Input High Voltage SHDN Input Low Voltage V V VOS VCM mV V mV
Note 2: DC output accuracy specifications refer to the trip level of the error amplifier. When pulse skipping, the output slightly rises (<0.5%) when transitioning from continuous conduction to no load. Note 3: On-time and minimum off-time specifications are measured from 50% to 50% at the DHM and DHS pins, with LX_ forced to GND, BST_ forced to 5V, and a 500pF capacitor from DH_ to LX_ to simulate external MOSFET gate capacitance. Actual incircuit times may be different due to MOSFET switching speeds. Note 4: The output fault-blanking time is measured from the time when FB reaches the regulation voltage set by the DAC code. During normal operation (SUS = GND), the regulation voltage is set by the VID DAC inputs (D0-D4). During suspend mode (SUS = REF or high), the regulation voltage is set by the suspend DAC inputs (S0-S1). Note 5: Specifications to TA = -40C and +100C are guaranteed by design and are not production tested.
8
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Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies MAX1544
Typical Operating Characteristics
(Circuit of Figure 1, VIN = 12V, VCC = VDD = 5V, SHDN = SKIP = VCC, D0-D4 set for 1.5V (SUS = GND), S0-S1 set for 1V (SUS = VCC), OFS = GND, TA = +25C, unless otherwise specified.)
OUTPUT VOLTAGE vs. LOAD CURRENT (VOUT = 1.50V)
MAX1544 toc01
EFFICIENCY vs. LOAD CURRENT (VOUT = 1.50V)
MAX1544 toc02
OUTPUT VOLTAGE vs. LOAD CURRENT (VOUT = 1.00V)
MAX1544 toc03
1.52 1.50 OUTPUT VOLTAGE (V) 1.48 1.46 1.44 1.42
100 VIN = 8V 90 EFFICIENCY (%)
1.02 1.00 OUTPUT VOLTAGE (V) 0.98 0.96 0.94 0.92 0.90
80 VIN = 12V VIN = 20V 60 SKIP = REF SKIP = VCC 0.1 1 10 100
70
1.40 1.38 0 10 20 30 40 50 60 LOAD CURRENT (A) 50
0
10
20
30
40
50
60
LOAD CURRENT (A)
LOAD CURRENT (A)
EFFICIENCY vs. LOAD CURRENT (VOUT = 1.00V)
MAX1544 toc04
OUTPUT VOLTAGE vs. LOAD CURRENT (VOUT = 0.80V)
MAX1544 toc05
DUAL-PHASE EFFICIENCY vs. LOAD CURRENT (VOUT = 0.80V)
SKIP = REF VIN = 8V 90 EFFICIENCY (%)
MAX1544 toc06
100 VIN = 8V 90 EFFICIENCY (%)
0.82 SUS = VCC 0.80 OUTPUT VOLTAGE (V)
100
80
0.78
80
70
VIN = 12V VIN = 20V SKIP = REF SKIP = VCC
0.76
70 VIN = 20V
VIN = 12V
60
0.74
60
50 0.1 1 10 100 LOAD CURRENT (A)
0.72 0 10 20 LOAD CURRENT (A) 30 40
50 0.1 1 10 100 LOAD CURRENT (A)
SINGLE-PHASE EFFICIENCY vs. LOAD CURRENT (VOUT = 0.80V)
MAX1544 toc07
SWITCHING FREQUENCY vs. LOAD CURRENT
MAX1544 toc08
NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE (FORCED-PWM MODE)
SKIP = VCC 120 SUPPLY CURRENT (mA) ICC + IDD 90
MAX1544 toc09
100 SKIP = GND 90 EFFICIENCY (%) VIN = 8V
400
150
SWITCHING FREQUENCY (kHz)
300 FORCED-PWM (SKIP = VCC) 200 SKIP MODE (SKIP = REF) 100 VOUT = 1V (NO LOAD)
80
70 VIN = 20V
VIN = 12V
60
60
30 IIN 0 0 10 20 LOAD CURRENT (A) 30 40 0 5 10 15 20 25 30 INPUT VOLTAGE (V) 0
50 0.1 1 10 100 LOAD CURRENT (A)
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9
Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies MAX1544
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 12V, VCC = VDD = 5V, SHDN = SKIP = VCC, D0-D4 set for 1.5V (SUS = GND), S0-S1 set for 1V (SUS = VCC), OFS = GND, TA = +25C, unless otherwise specified.)
NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE (PULSE SKIPPING)
MAX1544 toc10
OUTPUT OFFSET VOLTAGE vs. OFS VOLTAGE
MAX1544 toc11
REFERENCE VOLTAGE DISTRIBUTION
SAMPLE SIZE = 100 SAMPLE PERCENTAGE (%) 40
MAX1544 toc12
3.0 SKIP = REF 2.5 SUPPLY CURRENT (mA) 2.0 1.5 1.0 0.5 IIN 0 0 5 10 15 20 25 ICC + IDD
150 OUTPUT OFFSET VOLTAGE (mV) 100 50 0 -50 -100 -150 UNDEFINED REGION 0 0.5 1.0 OFS VOLTAGE (V) 1.5
50
30
20
10
30
2.0
0 1.990
1.995
INPUT VOLTAGE (V)
2.005 2.000 REFERENCE VOLTAGE (V)
2.010
CURRENT-BALANCE OFFSET VOLTAGE DISTRIBUTION
MAX1544 toc13
CURRENT-LIMIT THRESHOLD DISTRIBUTION
VILIM = 0.20V SAMPLE SIZE = 100 SAMPLE PERCENTAGE (%) 40
MAX1544 toc14
VOLTAGE-POSITIONING AMPLIFIER GAIN AND PHASE vs. FREQUENCY
60 50 40 30 GAIN (dB) GAIN
MAX1544 toc15
50 SAMPLE SIZE = 100 SAMPLE PERCENTAGE (%) 40
50
180 144 108 PHASE (DEGREES) 72 36 0 -36 -72
30
30
20 10 0 -10
20
20
10
10
-20 -30
PHASE
-108 -144
0 -2.50 -1.25 0 1.25 2.50 OFFSET VOLTAGE (mV)
0 9.0 9.5 10.0 10.5 11.0 CURRENT LIMIT (mV)
-40 0.1
1
10
100
1k
-180 10k
FREQUENCY (Hz)
VPS AMPLIFIER OFFSET VOLTAGE vs. COMMON-MODE VOLTAGE
160 OFFSET VOLTAGE (V) 140 120 100 80 60 40 20 0 0 1 2 3 4 5 COMMON-MODE VOLTAGE (V) VPS AMPLIFIER DISABLED
MAX1544 toc16
INDUCTOR CURRENT DIFFERENCE vs. LOAD CURRENT
MAX1544 toc17
180
1.0
0.8 IL(CS) - IL(CM) (A)
SKIP = REF
0.6 SKIP = VCC
0.4
0.2 RSENSE = 1m 0 0 10 20 30 40 50 LOAD CURRENT (A)
10
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Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies MAX1544
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 12V, VCC = VDD = 5V, SHDN = SKIP = VCC, D0-D4 set for 1.5V (SUS = GND), S0-S1 set for 1V (SUS = VCC), OFS = GND, TA = +25C, unless otherwise specified.)
POWER-UP SEQUENCE
MAX1544 toc18
SOFT-START
MAX1544 toc19
5V 5V A 0 2V 0 1V 0 5V C 0 0 1ms/div A. SHDN, 5V/div B. 1.5V OUTPUT, 1V/div C. VROK, 5V/div RTIME = 64.9k 100s/div A. SHDN, 5V/div B. 1.5V OUTPUT, 1V/div C. IL1, 10A/div D. IL2, 10A/div RLOAD = 75m, RTIME = 64.9k B 10A 0 C D 0 1.5V B A
SOFT-SHUTDOWN
MAX1544 toc20
1.50V LOAD TRANSIENT (10A TO 50A LOAD)
MAX1544 toc21
5V A 0 1.5V B 0
50A 10A 1.5V
A
B
20A 10A C 10A 0 200s/div A. SHDN, 5V/div B. 1.5V OUTPUT, 1V/div C. IL1, 10A/div D. IL2, 10A/div RLOAD = 75m, RTIME = 64.9k D 20A 0 0 20s/div A. LOAD CURRENT, (ILOAD = 10A TO 50A), 50A/div B. OUTPUT VOLTAGE (1.50V NO LOAD), 100mV/div C. IL1, 10A/div D. IL2, 10A/div C D
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11
Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies MAX1544
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 12V, VCC = VDD = 5V, SHDN = SKIP = VCC, D0-D4 set for 1.5V (SUS = GND), S0-S1 set for 1V (SUS = VCC), OFS = GND, TA = +25C, unless otherwise specified.)
1.00V LOAD TRANSIENT (10A TO 30A LOAD)
MAX1544 toc22
OFFSET TRANSITION
MAX1544 toc23
30A 10A 1.0V
A
0.2V 0
A
B
1.5V
B
10A 0 10A 0 20s/div A. LOAD CURRENT, (ILOAD = 10A TO 30A), 25A/div B. OUTPUT VOLTAGE (1.00V NO LOAD), 50mV/div C. IL1, 10A/div D. IL2, 10A/div C D 5A 5A 20s/div A. VOFS = 0 TO 200mV, 0.2V/div B. VOUT = 1.500V TO 1.475, 20mV/div C. IL1, 10A/div D. IL2, 10A/div 10A LOAD C D
SUSPEND TRANSITION (DUAL-PHASE PWM OPERATION)
MAX1544 toc24
SUSPEND TRANSITION (SINGLE-PHASE SKIP OPERATION)
MAX1544 toc25
3.3V 0 1.5V
A
3.3V 0 1.5V
A
B 1.0V 1.0V 10A 2.5A 2.5A C 0 D 10A
B
C
D 0 40s/div A. SUS, 5V/div B. VOUT = 1.5V TO 1.0V, 0.5V/div C. IL1, 10A/div D. IL2, 10A/div 5A LOAD, SKIP = VCC, RTIME = 64.9k 100s/div A. SUS, 5V/div B. VOUT = 1.5V TO 1.0V, 0.5V/div C. IL1, 10A/div D. IL2, 10A/div 5A LOAD, COUT = (4) 680F, SKIP = SUS, RTIME = 64.9k
12
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Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies MAX1544
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 12V, VCC = VDD = 5V, SHDN = SKIP = VCC, D0-D4 set for 1.5V (SUS = GND), S0-S1 set for 1V (SUS = VCC), OFS = GND, TA = +25C, unless otherwise specified.)
SINGLE-PHASE SKIP TO DUAL-PHASE PWM TRANSITION
MAX1544 toc26
DUAL-PHASE SKIP TO DUAL-PHASE PWM TRANSITION
MAX1544 toc27
5V A 1.5V B
5V 2V 1.5V
A B
0
C
0
C
0
D
0
D
20s/div A. SKIP = VCC TO GND, 5V/div B. 1.5V OUTPUT, 50mV/div C. IL1, 10A/div D. IL2, 10A/div 2A LOAD
20s/div A. SKIP = VCC TO REF, 5V/div B. 1.5V OUTPUT, 50mV/div C. IL1, 10A/div D. IL2, 10A/div 2A LOAD
100mV DAC CODE TRANSITION
MAX1544 toc28
400mV DAC CODE TRANSITION
MAX1544 toc29
3.3V 0 1.5V B 1.4V 5A 5A C A
3.3V 0 1.5V 1.1V B A
5A 5A
C
D
D
20s/div A. D1, 5V/div B. VOUT = 1.50V TO 1.40V, 100mV/div C. IL1, 10A/div D. IL2, 10A/div 10A LOAD
40s/div A. D3, 5V/div B. VOUT = 1.50V TO 1.10V, 0.5V/div C. IL1, 10A/div D. IL2, 10A/div 10A LOAD
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13
Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies MAX1544
Pin Description
PIN 1 NAME TIME FUNCTION Slew-Rate Adjustment Pin. Connect a resistor from TIME to GND to set the internal slew-rate clock. A 150k to 15k resistor sets the clock from 100kHz to 1MHz, fSLEW = 500kHz x 30k/RTIME. On-Time Selection Control Input. This four-level input sets the K-factor value used to determine the DH_ on-time (see the On-Time One-Shot (TON) section): GND = 550kHz, REF = 300kHz, OPEN = 200kHz, VCC = 100kHz Suspend Input. SUS is a three-level logic input. When the controller detects on-transition on SUS, the controller slews the output voltage to the new voltage level determined by SUS, S0-S1, and D0-D4. The controller blanks VROK during the transition and another 24 RTIME clock cycles after the new DAC code is reached. Connect SUS as follows to select which multiplexer sets the nominal output voltage: 3.3V or VCC (high) = Suspend mode; S0-S1 low-range suspend code (Table 5) REF = Suspend mode; S0-S1 high-range suspend code (Table 5) GND = Normal operation; D0-D4 VID DAC code (Table 4) Suspend-Mode Voltage Select Inputs. S0-S1 are four-level digital inputs that select the suspend mode VID code (Table 5) for the suspend mode multiplexer inputs. If SUS is high, the suspend mode VID code is delivered to the DAC (see the Internal Multiplexers section), overriding any other voltage setting (Figure 3). Shutdown Control Input. This input cannot withstand the battery voltage. Connect to VCC for normal operation. Connect to ground to put the IC into its 1A (typ) shutdown state. During the transition from normal operation to shutdown, the output voltage ramps down at 4 times the output-voltage slew rate programmed by the TIME pin. In shutdown mode, DLM and DLS are forced to VDD to clamp the output to ground. Forcing SHDN to 12V ~ 15V disables both overvoltage protection and undervoltage protection circuits, disables overlap operation, and clears the fault latch. Do not connect SHDN to >15V. Voltage-Divider Input for Offset Control. For 0 < VOFS < 0.8V, 0.125 times the voltage at OFS is subtracted from the output. For 1.2V < VOFS < 2V, 0.125 times the difference between REF and OFS is added to the output. Voltages in the range of 0.8V < VOFS < 1.2V are undefined. The controller disables the offset amplifier during suspend mode (SUS = REF or high). 2V Reference Output. Bypass to GND with 0.22F or greater ceramic capacitor. The reference can source 100A for external loads. Loading REF degrades output voltage accuracy according to the REF load regulation error. Current-Limit Adjustment. The current-limit threshold defaults to 30mV if ILIM is tied to VCC. In adjustable mode, the current-limit threshold voltage is precisely 1/20 the voltage seen at ILIM over a 0.2V to 1.5V range. The logic threshold for switchover to the 30mV default value is approximately VCC - 1V. Analog Supply Voltage Input for PWM Core. Connect VCC to the system supply voltage (4.5V to 5.5V) with a series 10 resistor. Bypass to GND with a 1F or greater ceramic capacitor, as close to the IC as possible. Analog Ground. Connect the MAX1544's exposed pad to analog ground. Voltage Integrator Capacitor Connection. Connect a 47pF to 1000pF (47pF typ) capacitor from CCV to analog ground (GND) to set the integration time constant. Ground Remote-Sense Input. Connect GNDS directly to the CPU ground-sense pin. GNDS internally connects to an amplifier that adjusts the output voltage, compensating for voltage drops from the regulator ground to the load ground.
2
TON
3
SUS
4, 5
S0, S1
6
SHDN
7
OFS
8
REF
9
ILIM
10 11 12
VCC GND CCV
13
GNDS
14
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Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies
Pin Description (continued)
PIN 14 15 NAME CCI FB FUNCTION Current Balance Compensation. Connect a 470pF capacitor between CCI and FB. See the Current Balance Compensation section. Feedback Input. FB is internally connected to both the feedback input and the output of the voltagepositioning op amp. See the Setting Voltage Positioning section to set the voltage-positioning gain. Op Amp Inverting Input and Op Amp Disable Input. When using the internal op amp for additional voltage-positioning gain, connect to the negative terminal of current-sense resistor through a resistor as described in the Setting Voltage Positioning section. Connect OAIN- to VCC to disable the op amp. The logic threshold to disable the op amp is approximately VCC - 1V. Op Amp Noninverting Input. When using the internal op amp for additional voltage-positioning gain, connect to the positive terminal of current-sense resistor through a resistor as described in the Setting Voltage Positioning section. Pulse-Skipping Select Input. When pulse skipping, the controller blanks the VROK upper threshold: 3.3V or VCC (high) = Dual-phase forced-PWM operation REF = Dual-phase pulse-skipping operation GND = Single-phase pulse-skipping operation Overvoltage Protection Enable Input. Connect OVP to VCC to enable the output overvoltage fault protection. Connect OVP to GND to disable the output overvoltage fault protection. During normal forced-PWM operation (SKIP = high), the controller detects an OVP fault if the output voltage exceeds the set DAC voltage by more than 13% (min). During pulse-skipping operation (SKIP = REF or GND), the controller detects an OVP fault if the output voltage exceeds the fixed 2V (typ) threshold. If an overvoltage fault occurs, the controller is immediately shutdown and the output is discharged. See the Fault Protection section. Low-Voltage VID DAC Code Inputs. The D0-D4 inputs do not have internal pullups. These 1.0V logic inputs are designed to interface directly with the CPU. In normal mode (Table 4, SUS = GND), the output voltage is set by the VID code indicated by the logic-level voltages on D0-D4. In suspend mode (Table 5, SUS = REF or high), the decoded state of the four-level S0-S1 inputs sets the output voltage. Open-Drain Power-Good Output. After output voltage transitions, except during power-up and powerdown, if OUT is in regulation then VROK is high impedance. The controller blanks VROK whenever the slew rate control is active (output voltage transitions). VROK is forced low in shutdown. A pullup resistor on VROK causes additional finite shutdown current. During power-up, VROK includes a 3ms (min) delay after the output reaches the regulation voltage. Main Boost Flying Capacitor Connection. An optional resistor in series with BSTM allows the DHM pullup current to be adjusted. Main Inductor Connection. LXM is the internal lower supply rail for the DHM high-side gate driver. Main High-Side Gate-Driver Output. Swings LXM to BSTM. Main Low-Side Gate-Driver Output. DLM swings from PGND to VDD. DLM is forced high after the MAX1544 powers down. Supply Voltage Input for the DLM and DLS Gate Drivers. Connect to the system supply voltage (4.5V to 5.5V). Bypass VDD to PGND with a 2.2F or greater ceramic capacitor as close to the IC as possible. Power Ground. Ground connection for low-side gate drivers DLM and DLS.
MAX1544
16
OAIN-
17
OAIN+
18
SKIP
19
OVP
20-24
D4-D0
25
VROK
26 27 28 29
BSTM LXM DHM DLM
30 31
VDD PGND
______________________________________________________________________________________
15
Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies MAX1544
Pin Description (continued)
PIN 32 33 34 35 36 37 38 39 40 NAME DLS DHS LXS BSTS V+ CMP CMN CSN CSP FUNCTION Secondary Low-Side Gate-Driver Output. DLS swings from PGND to VDD. DLS is forced high after the MAX1544 powers down. Secondary High-Side Gate-Driver Output. Swings LXS to BSTS. Secondary Inductor Connection. LXS is the internal lower supply rail for the DHS high-side gate driver. Secondary Boost Flying Capacitor Connection. An optional resistor in series with BSTS allows the DHS pullup current to be adjusted. Battery Voltage-Sense Connection. Used only for PWM one-shot timing. DH_ on-time is inversely proportional to input voltage over a range of 4V to 28V. Main Inductor Positive Current-Sense Input Main Inductor Negative Current-Sense Input Secondary Inductor Positive Current-Sense Input Secondary Inductor Negative Current-Sense Input
Detailed Description
Dual 180 Out-of-Phase Operation
The two phases in the MAX1544 operate 180 out-ofphase (SKIP = REF or high) to minimize input and output filtering requirements, reduce electromagnetic interference (EMI), and improve efficiency. This effectively lowers component count--reducing cost, board space, and component power requirements--making the MAX1544 ideal for high-power, cost-sensitive applications. Typically, switching regulators provide transfer power using only one phase instead of dividing the power among several phases. In these applications, the input capacitors must support high-instantaneous current requirements. The high-RMS ripple current can lower efficiency due to I2R power loss associated with the input capacitor's effective series resistance (ESR). Therefore, the system typically requires several low-ESR input capacitors in parallel to minimize input voltage ripple, to reduce ESR-related power losses, and to meet the necessary RMS ripple current rating. With the MAX1544, the controller shares the current between two phases that operate 180 out-of-phase, so the high-side MOSFETs never turn on simultaneously during normal operation. The instantaneous input current of either phase is effectively cut in half, resulting in
reduced input voltage ripple, ESR power loss, and RMS ripple current (see the Input Capacitor Selection section). As a result, the same performance can be achieved with fewer or less-expensive input capacitors. Table 1 lists component selection for standard multiphase selections and Table 2 is a list of component suppliers.
Transient Overlap Operation
When a transient occurs, the response time of the controller depends on how quickly it can slew the inductor current. Multiphase controllers that remain 180 degrees out-of-phase when a transient occurs actually respond slower than an equivalent single-phase controller. In order to provide fast transient response, the MAX1544 supports a phase-overlap mode, which allows the dual regulators to operate in-phase when heavy-load transients are detected, reducing the response time. After either high-side MOSFET turns off, if the output voltage does not exceed the regulation voltage when the minimum off-time expires, the controller simultaneously turns on both high-side MOSFETs during the next ontime cycle. This maximizes the total inductor current slew rate. The phases remain overlapped until the output voltage exceeds the regulation voltage after the minimum off-time expires.
16
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Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies MAX1544
Table 1. Component Selection for Standard Multiphase Applications
DESIGNATION Input Voltage Range VID Output Voltage (D4-D0) Suspend Voltage (SUS, S0-S1) Maximum Load Current Number of Phases (TOTAL) Inductor (per Phase) Switching Frequency High-Side MOSFET (NH, per phase) Low-Side MOSFET (NL, per phase) Total Input Capacitance (CIN) Total Output Capacitance (COUT) Current-Sense Resistor (RSENSE, per Phase) MAX1544 AMD MOBILE COMPONENTS Circuit of Figure 1 7V to 24V 1.5V (D4-D0 = 00010) Not used (SUS = GND) 60A Two phases (1) MAX1544 0.6H Panasonic ETQP1H0R6BFA 300kHz (TON = REF) Siliconix (1) Si7886DP or International Rectifier (2) IRF6604 Siliconix (2) Si7442DP or International Rectifier (2) IRF6603 (8) 10F, 25V Taiyo Yuden TMK432BJ106KM or TDK C4532X5R1E106M (4) 680F, 2.5V Sanyo 2R5TPD680M 1m Panasonic ERJM1WTJ1M0U MAX1544 AMD DESKTOP COMPONENTS Circuit of Figure 12 7V to 24V 1.5V (D4-D0 = 00010) Not used (SUS = GND) 70A Four phases (1) MAX1544 + (2) MAX1980 0.7H Panasonic ETQP2H0R7BFA or 0.8H Sumida CDEP105L-0R8 300kHz (TON = REF) International Rectifier (1) IRF7811W or Fairchild (1) FDS6694 Fairchild (2) FDS6688 or Siliconix (1) Si7442DP (8) 10F, 25V Taiyo Yuden TMK432BJ106KM or TDK C4532X5R1E106M (5) 680F, 2.5V Sanyo 2R5TPD680M 1m Panasonic ERJM1WTJ1M0U
After the phase-overlap mode ends, the controller automatically begins with the opposite phase. For example, if the secondary phase provided the last on-time pulse before overlap operation began, the controller starts switching with the main phase when overlap operation ends.
For the MAX1544, the slew-rate controller ramps up the output voltage in 25mV increments to the proper operating voltage (see Tables 3 and 4) set by either D0-D4 (SUS = GND) or S0-S1 (SUS = REF or high). The ramp rate is set with the RTIME resistor (see the Output Voltage Transition Timing section). The ramp rate is set with the RTIME resistor (see the Output Voltage Transition Timing section). The controller pulls VROK low until at least 3ms after the MAX1544 reaches the target DAC code.
Power-Up Sequence
The MAX1544 is enabled when SHDN is driven high (Figure 2). The reference powers up first. Once the reference exceeds its UVLO threshold, the PWM controller evaluates the DAC target and starts switching.
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17
Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies MAX1544
C1 2.2F VDD VCC MAX1544 VROK D0 D1 D2 D3 D4 S0 S1 SHDN RTIME 64.9k TIME CCCV 47pF CCV OUTPUT CREF 0.22F REF (300kHz) TON REF R8 R9 49.9k 100k 1% 1% ILIM FB CCCI 470pF CCI CSP CSN BSTS CBST2 0.22F OFS R7 158k 1% OVP SKIP SUS POWER GROUND ANALOG GROUND *LOWER INPUT VOLTAGES REQUIRE ADDITIONAL INPUT CAPACITANCE. GNDS DHS LXS DLS VCC (OVP ENABLED) PWM SKIP COUT NL2 NH2 L2 RSENSE2 1.0m R1 1.5k 1% R4 1k 1% GND CMN CMP OAIN+ OAINV+ BSTM CBST1 0.22F DHM LXM DLM SUSPEND INPUTS (FOUR-LEVEL LOGIC) ON OFF PGND R2 1k 1% NL1 R3 1k 1% R10 1.5k 1% NH1 L1 RSENSE1 1.0m COUT BST DIODES INPUT* 7V TO 24V 5V BIAS SUPPLY
R12 100k
R13 10 C2 1F
POWER GOOD
CIN
DAC INPUTS
R5 1k 1%
REF C3 100pF
R6 30.1k 1%
CIN
Figure 1. Standard Two-Phase AMD Mobile 60A Application Circuit
18
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Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies MAX1544
SHDN
VID (D0-D4) SOFT-START 1 LSB PER RTIME CYCLE VCORE
DO NOT CARE SOFT-SHUTDOWN 1 LSB PER 4 RTIME CYCLES
VROK tVROK(START) 3ms (TYP)
Figure 2. Power-Up and Shutdown Sequence Timing Diagram
Table 2. Component Suppliers
MANUFACTURER BI Technologies Central Semiconductor Coilcraft Coiltronics Fairchild Semiconductor International Rectifier Kemet Panasonic Sanyo Siliconix (Vishay) Sumida Taiyo Yuden TDK TOKO PHONE 714-447-2345 (USA) 631-435-1110 (USA) 800-322-2645 (USA) 561-752-5000 (USA) 888-522-5372 (USA) 310-322-3331 (USA) 408-986-0424 (USA) 847-468-5624 (USA) 65-6281-3226 (Singapore) 203-268-6261 (USA) 408-982-9660 (USA) 03-3667-3408 (Japan) 408-573-4150 (USA) 847-803-6100 (USA) 81-3-5201-7241 (Japan) 858-675-8013 (USA) www.centralsemi.com www.coilcraft.com www.coiltronics.com www.fairchildsemi.com www.irf.com www.kemet.com www.panasonic.com www.secc.co.jp www.vishay.com www.sumida.com www.t-yuden.com www.component.tdk.com www.tokoam.com WEBSITE www.bitechnologies.com
Shutdown
When SHDN goes low, the MAX1544 enters low-power shutdown mode. VROK is pulled low immediately, and the output voltage ramps down to 0V in LSB increments at 4 times the clock rate set by RTIME: t SHDN VDAC fSLEW VLSB 4
where fSLEW = 500kHz 30k/RTIME, VDAC is the DAC setting when the controller begins the shutdown sequence, and VLSB = 25mV is the DAC's smallest voltage increment. Slowly discharging the output capacitors by slewing the output over a long period of time (4/fSLEW) keeps the average negative inductor current low (damped response), thereby eliminating the negative output voltage excursion that occurs when the controller discharges the output quickly by permanently turning on the low-side MOSFET (underdamped response).
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19
Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies MAX1544
Table 3. Operating Mode Truth Table
SHDN SUS SKIP OFS OUTPUT VOLTAGE GND D0-D4 (No offset) OPERATING MODE Low-Power Shutdown Mode. DL_ is forced high, DH_ is forced low, and the PWM controller is disabled. The supply current drops to 1A (typ). Normal Operation. The no-load output voltage is determined by the selected VID DAC code (D0-D4, Table 4). Pulse-Skipping Operation. When SKIP is pulled low, the MAX1544 immediately enters pulse-skipping operation allowing automatic PWM/PFM switchover under light loads. The VROK upper threshold is blanked. Deep-Sleep Mode. The no-load output voltage is determined by the selected VID DAC code (D0-D4, Table 4) plus the offset voltage set by OFS. Suspend Mode. The no-load output voltage is determined by the selected suspend code (SUS, S0-S1, Table 5), overriding all other active modes of operation. Fault Mode. The fault latch has been set by either UVP, OVP, or thermal shutdown. The controller remains in FAULT mode until VCC power is cycled or SHDN toggled.
GND
x
x
x
VCC
GND
VCC
GND or REF
VCC
x
GND or REF
GND or REF
D0-D4 (No offset)
VCC
GND
x
0 to 0.8V or 1.2V to 2V
D0-D4 (Plus offset)
VCC
REF or High x
x
x
SUS, S0-S1 (No offset)
VCC
x
x
GND
This eliminates the need for the Schottky diode normally connected between the output and ground to clamp the negative output voltage excursion. When the DAC reaches the 0V setting, DL_ goes high, DH_ goes low, the reference turns off, and the supply current drops to about 1A. When a fault condition--output undervoltage lockout, output overvoltage lockout (OVP = VCC), or thermal shutdown--activates the shutdown sequence, the controller sets the fault latch to prevent the controller from restarting. To clear the fault latch and reactivate the controller, toggle SHDN or cycle VCC power below 1V. When SHDN goes high, the reference powers up. Once the reference voltage exceeds its UVLO threshold, the controller evaluates the DAC target and starts switching. The slew-rate controller ramps up from 0V in LSB increments to the currently selected output-voltage setting (see the Power-Up Sequence section). There is no traditional soft-start (variable current-limit) circuitry, so full output current is available immediately.
DAC Inputs (D0-D4)
During normal forced-PWM operation (SUS = GND), the digital-to-analog converter (DAC) programs the output voltage using the D0-D4 inputs. Do not leave D0-D4 unconnected. D0-D4 can be changed while the MAX1544 is active, initiating a transition to a new output voltage level. Change D0-D4 together, avoiding greater than 1s skew between bits. Otherwise, incorrect DAC readings can cause a partial transition to the wrong voltage level followed by the intended transition to the correct voltage level, lengthening the overall transition time. The available DAC codes and resulting output voltages are compatible with AMD Hammer voltage specifications (Table 4).
Four-Level Logic Inputs
TON and S0-S1 are four-level logic inputs. These inputs help expand the functionality of the controller without adding an excessive number of pins. The fourlevel inputs are intended to be static inputs. When left open, an internal resistive voltage-divider sets the input voltage to approximately 3.5V. Therefore, connect the four-level logic inputs directly to VCC, REF, or GND when selecting one of the other logic levels. See the Electrical Characteristics for exact logic level voltages.
Internal Multiplexers
The MAX1544 has a unique internal DAC input multiplexer (muxes) that selects one of three different DAC code settings for different processor states (Figure 3). On startup, the MAX1544 selects the DAC code from the D0-D4 (SUS = GND) or S0-S1 (SUS = REF or high) input decoders.
20
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Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies MAX1544
D0 D1 D2 D3 D4 D0-D4 DECODER SUSPEND MUX IN OUT 0
S0-S1 DECODER S0 S1 IN SEL SEL OUT 1 OUT DAC
SUS 2.5V SUS 3-LEVEL DECODER
1.0V
Figure 3. Internal Multiplexers Functional Diagram
Suspend Mode
When the processor enters low-power suspend mode, it sets the regulator to a lower output voltage to reduce power consumption. The MAX1544 includes independent suspend-mode output voltage codes set by the four-level S0-S1 inputs and the three-level SUS input. When the CPU suspends operation (SUS = REF or high), the controller disables the offset amplifier and overrides the 5-bit VID DAC code set by either D0-D4 (normal operation). The master controller slews the output to the selected suspend-mode voltage. During the transition, the MAX1544 blanks VROK and the UVP fault protection until 24 RTIME clock cycles after the slew-rate controller reaches the suspend-mode voltage. SUS is a three-level logic input: GND, REF, or high. This expands the functionality of the controller without adding an additional pin. This input is intended to be driven by a dedicated open-drain output with the pullup resistor connected either to REF (or a resistive divider from V CC ) or to a logic-level bias supply (3.3V or greater). When pulled up to REF, the MAX1544 selects the upper suspend voltage range. When pulled high (2.7V or greater), the controller selects the lower suspend voltage range. See the Electrical Characteristics for exact logic level voltages.
Output Voltage Transition Timing
The MAX1544 is designed to perform mode transitions in a controlled manner, automatically minimizing input surge currents. This feature allows the circuit designer to achieve nearly ideal transitions, guaranteeing just-in-time arrival at the new output voltage level with the lowest possible peak currents for a given output capacitance. At the beginning of an output voltage transition, the MAX1544 blanks the VROK output, preventing it from changing states. VROK remains blanked during the transition and is enabled 24 clock cycles after the slew-rate controller has set the final DAC code value. The slew-rate clock frequency (set by resistor RTIME) must be set fast enough to ensure that the transition is completed within the maximum allotted time. The slew-rate controller transitions the output voltage in 25mV steps during soft-start, soft-shutdown, and suspend-mode transitions. The total time for a transition depends on R TIME , the voltage difference, and the accuracy of the MAX1544's slew-rate clock, and is not dependent on the total output capacitance. The greater the output capacitance, the higher the surge current required for the transition. The MAX1544 automatically controls the current to the minimum level required to complete the transition in the calculated time, as long
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21
Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies MAX1544
SUS 1 LSB PER RTIME CYCLE VDAC OUTPUT SET BY SUS AND S0-S1 OUTPUT SET BY D0-D4
tSLEW TIME CLOCK
tBLANK = 24 CLKS
tSLEW
tBLANK = 24 CLKS
VROK VROK BLANKING VROK BLANKING
Figure 4. Suspend Transition
as the surge current is less than the current limit set by ILIM. The transition time is given by: VOLD - VNEW t SLEW for VOUT risin g fSLEW VLSB 1 VOLD - VNEW t SLEW + 2 for VOUT falling fSLEW VLSB 1 where fSLEW = 500kHz 30k / RTIME, VOLD is the original DAC setting, VNEW is the new DAC setting, and VLSB = 25mV is the DAC's smallest voltage increment. The additional two clock cycles on the falling edge time are due to internal synchronization delays. See TIME Frequency Accuracy in the Electrical Characteristics for fSLEW limits. The practical range of RTIME is 15k to 150k, corresponding to 1.0s to 10s per 25mV step. Although the DAC takes discrete steps, the output filter makes the transitions relatively smooth. The average inductor current required to make an output voltage transition is: IL COUT x VLSB x fSLEW
Fault Protection
Output Overvoltage Protection The MAX1544 features selectable output OVP. Connect OVP to VCC to enable the output overvoltage-fault protection. The OVP circuit is designed to protect the CPU against a shorted high-side MOSFET by drawing high current and blowing the battery fuse. The MAX1544 continuously monitors the output for an overvoltage fault. During normal forced-PWM operation (SKIP = high), the controller detects an OVP fault if the output voltage exceeds the set DAC voltage by more than 13% (min). During pulse-skipping operation (SKIP = REF or GND), the controller detects an OVP fault if the output voltage exceeds the fixed 2.0V (typ) threshold. When the OVP circuit detects an overvoltage fault, it immediately sets the fault latch and activates the shutdown sequence. This action discharges the output filter capacitor and forces the output to ground. If the condition that caused the overvoltage (such as a shorted high-side MOSFET) persists, the battery fuse blows. The controller remains shut down until the fault latch is cleared by toggling SHDN or cycling the VCC power supply below 1V. To disable the overvoltage protection, connect OVP to GND. The OVP is also disabled when the controller is in the no-fault test mode (see the No-Fault Test Mode section).
22
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Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies MAX1544
Table 4. Output Voltage VID DAC Codes (SUS = GND)
D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 OUTPUT VOLTAGE (V) 1.550 1.525 1.500 1.475 1.450 1.425 1.400 1.375 1.350 1.325 1.300 1.275 1.250 1.225 1.200 1.175 D4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 OUTPUT VOLTAGE (V) 1.150 1.125 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925 0.900 0.875 0.850 0.825 0.800 Shutdown
Output Undervoltage Shutdown The output UVP function is similar to foldback current limiting, but employs a timer rather than a variable current limit. If the MAX1544 output voltage is under 70% of the nominal value, the controller activates the shutdown sequence and sets the fault latch. Once the controller ramps down to the 0V DAC code setting, it forces the DL_ low-side gate driver high and pulls the DH_ high-side gate driver low. Toggle SHDN or cycle the VCC power supply below 1V to clear the fault latch and reactivate the controller. UVP is ignored during output voltage transitions and remains blanked for an additional 24 clock cycles after the controller reaches the final DAC code value. UVP can be disabled through the no-fault test mode (see the No-Fault Test Mode section). Thermal-Fault Protection The MAX1544 features a thermal-fault protection circuit. When the junction temperature rises above +160C, a thermal sensor activates the fault latch and the softshutdown sequence. Once the controller ramps down to the 0V DAC code setting, it forces the DL_ low-side gate driver high, and pulls the DH_ high-side gate driver low. Toggle SHDN or cycle the VCC power supply below 1V to clear the fault latch and reactivate the controller after the junction temperature cools by 15C. Thermal shutdown can be disabled through the no-fault test mode (see the No-Fault Test Mode section).
No-Fault Test Mode The latched-fault protection features and overlap mode can complicate the process of debugging prototype breadboards since there are (at most) a few milliseconds in which to determine what went wrong. Therefore, a nofault test mode is provided to disable the fault protection (overvoltage protection, undervoltage protection, and thermal shutdown) and overlap mode. Additionally, the test mode clears the fault latch if it has been set. The nofault test mode is entered by forcing 12V to 15V on SHDN.
Multiphase Quick-PWM
5V Bias Supply (VCC and VDD)
The Quick-PWM controller requires an external 5V bias supply in addition to the battery. Typically, this 5V bias supply is the notebook's 95%-efficient 5V system supply. Keeping the bias supply external to the IC improves efficiency and eliminates the cost associated with the 5V linear regulator that would otherwise be needed to supply the PWM circuit and gate drivers. If stand-alone capability is needed, the 5V bias supply can be generated with an external linear regulator. The 5V bias supply must provide VCC (PWM controller) and VDD (gate-drive power), so the maximum current drawn is: IBIAS = ICC + fSW(QG(LOW) + QG(HIGH))
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23
Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies MAX1544
BSTS CSN CSP ILIM Q TRIG ON-TIME ONE-SHOT R CMP CMN VCC REF MINIMUM OFF-TIME Q TRIG Gm ONE-SHOT FB ON-TIME ONE-SHOT REF (2.0V) T SHDN GND Q R Q S S CMP CCV Gm REF 1.0V SKIP FAULT T T=1 PGND DLM CMN 1.5mV VDD Q R MAIN PHASE DRIVERS BSTM DHM LXM Q Q TRIG CSP V+ CSN Gm CMN CCI CMP SECONDARY PHASE DRIVERS DHS LXS DLS
19R
TON
T=0 Gm OFS FB OAIN+ Gm OAINGNDS R-2R DAC INTERNAL MULTIPLEXERS, MODE CONTROL, AND SLEW-RATE CONTROL TIME
MAX1544
S[0:1] D[0:4]
SUS
SKIP
Figure 5. Dual-Phase Quick-PWM Functional Diagram 24 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies MAX1544
Table 5. Suspend Mode DAC Codes
LOWER SUSPEND CODES SUS* High High High High High High High High High High High High High High High High S1 GND GND GND GND REF REF REF REF OPEN OPEN OPEN OPEN VCC VCC VCC VCC S0 GND REF OPEN VCC GND REF OPEN VCC GND REF OPEN VCC GND REF OPEN VCC OUTPUT VOLTAGE (V) 0.675 0.700 0.725 0.750 0.775 0.800 0.825 0.850 0.875 0.900 0.925 0.950 0.975 1.000 1.025 1.050 SUS* REF REF REF REF REF REF REF REF REF REF REF REF REF REF REF REF UPPER SUSPEND CODES S1 GND GND GND GND REF REF REF REF OPEN OPEN OPEN OPEN VCC VCC VCC VCC S0 GND REF OPEN VCC GND REF OPEN VCC GND REF OPEN VCC GND REF OPEN VCC OUTPUT VOLTAGE (V) 1.075 1.100 1.125 1.150 1.175 1.200 1.225 1.250 1.275 1.300 1.325 1.350 1.375 1.400 1.425 1.450
*Connect the three-level SUS input to a 2.7V or greater supply (3.3V or VCC) for an input logic level high.
where ICC is provided in the Electrical Characteristics, f SW is the switching frequency, and Q G(LOW) and QG(HIGH) are the MOSFET data sheet's total gate-charge specification limits at VGS = 5V. V+ and VDD can be tied together if the input power source is a fixed 4.5V to 5.5V supply. If the 5V bias supply is powered up prior to the battery supply, the enable signal (SHDN going from low to high) must be delayed until the battery voltage is present to ensure startup.
Another one-shot sets a minimum off-time. The on-time one-shot triggers when the error comparator goes low, the inductor current of the selected phase is below the valley current-limit threshold, and the minimum off-time one-shot times out. The controller maintains 180 out-ofphase operation by alternately triggering the main and secondary phases after the error comparator drops below the output voltage set point.
On-Time One-Shot (TON)
The core of each phase contains a fast, low-jitter, adjustable one-shot that sets the high-side MOSFETs on-time. The one-shot for the main phase varies the ontime in response to the input and feedback voltages. The main high-side switch on-time is inversely proportional to the input voltage as measured by the V+ input, and proportional to the feedback voltage (VFB): t ON(MAIN) = K (VFB + 0.075V)
VIN
Free-Running, Constant-On-Time PWM Controller with Input Feed Forward
The Quick-PWM control architecture is a pseudofixedfrequency, constant-on-time, current-mode regulator with input voltage feed forward (Figure 5). This architecture relies on the output filter capacitor's ESR to act as the current-sense resistor, so the output ripple voltage provides the PWM ramp signal. The control algorithm is simple: the high-side switch on-time is determined solely by a one-shot whose period is inversely proportional to input voltage, and directly proportional to output voltage or the difference between the main and secondary inductor currents (see the On-Time One-Shot (TON) section).
where K is set by the TON pin-strap connection (Table 6) and 0.075V is an approximation to accommodate the expected drop across the low-side MOSFET switch.
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Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies MAX1544
The one-shot for the secondary phase varies the on-time in response to the input voltage and the difference between the main and secondary inductor currents. Two identical transconductance amplifiers integrate the difference between the master and slave current-sense signals. The summed output is internally connected to CCI, allowing adjustment of the integration time constant with a compensation network connected between CCI and FB. The resulting compensation current and voltage are determined by the following equations: ICCI = GM (VCMP - VCMN ) - GM (VCSP - VCSN ) VCCI = VFB + ICCIZ CCI where ZCCI is the impedance at the CCI output. The secondary on-time one-shot uses this integrated signal (VCCI) to set the secondary high-side MOSFETs on-time. When the main and secondary current-sense signals (VCM = VCMP - VCMN and VCS = VCSP - VCSM) become unbalanced, the transconductance amplifiers adjust the secondary on-time, which increases or decreases the secondary inductor current until the current-sense signals are properly balanced: V + 0.075V t ON(2ND) = K CCI VIN V ICCIZ CCI + 0.075V = K FB + K V VIN IN = (Main on - time) + (Secondary Current Balance Correction) This algorithm results in a nearly constant switching frequency and balanced inductor currents, despite the lack of a fixed-frequency clock generator. The benefits of a constant switching frequency are twofold: first, the frequency can be selected to avoid noise-sensitive regions such as the 455kHz IF band; second, the inductor ripple-current operating point remains relatively constant, resulting in easy design methodology and predictable output-voltage ripple. The on-time one-shots have good accuracy at the operating points specified in the Electrical Characteristics. On-times at operating points far removed from the conditions specified in the Electrical Characteristics can vary over a wider range. For example, the 300kHz setting typically runs about 3% slower with inputs much greater than 12V due to the very short on-times required. On-times translate only roughly to switching frequencies. The on-times guaranteed in the Electrical Characteristics are influenced by switching delays in the external highside MOSFET. Resistive losses, including the inductor,
26
both MOSFETs, output capacitor ESR, and PC board copper losses in the output and ground tend to raise the switching frequency at higher output currents. Also, the dead-time effect increases the effective on-time, reducing the switching frequency. It occurs only during forcedPWM operation and dynamic output voltage transitions when the inductor current reverses at light or negative load currents. With reversed inductor current, the inductor's EMF causes LX to go high earlier than normal, extending the on-time by a period equal to the DH-rising dead time. For loads above the critical conduction point, where the dead-time effect is no longer a factor, the actual switching frequency (per phase) is: fSW =
tON (VIN + VDROP1 - VDROP2 )
(VOUT + VDROP1)
where VDROP1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PC board resistances; VDROP2 is the sum of the parasitic voltage drops in the inductor charge path, including high-side switch, inductor, and PC board resistances; and tON is the on-time as determined above.
Current Balance
Without active current-balance circuitry, the current matching between phases depends on the MOSFET's on-resistance (RDS(ON)), thermal ballasting, on-/off-time matching, and inductance matching. For example, variation in the low-side MOSFET on-resistance (ignoring thermal effects) results in a current mismatch that is proportional to the on-resistance difference: R IMAIN - I2ND = IMAIN 1- MAIN R2ND However, mismatches between on-times, off-times, and inductor values increase the worst-case current imbalance, making it impossible to passively guarantee accurate current balancing.
Table 6. Approximate K-Factor Errors
TON CONNECTION VCC Float REF GND FREQUENCY SETTING (kHz) 100 200 300 550 K-FACTOR (s) 10 5 3.3 1.8 MAX K-FACTOR ERROR (%) 10 10 10 12.5
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Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies
The multiphase Quick-PWM controller integrates the difference between the current-sense voltages and adjusts the on-time of the secondary phase to maintain current balance. The current balance now relies on the accuracy of the current-sense resistors instead of the inaccurate, thermally sensitive on-resistance of the lowside MOSFETs. With active current balancing, the current mismatch is determined by the current-sense resistor values and the offset voltage of the transconductance amplifiers: IOS(IBAL) = ILM - ILS = VOS(IBAL) RSENSE The controller also uses the amplifier for remote output sensing (FBS) by summing in the remote-sense voltage into the positive terminal of the voltage-positioning amplifier (Figure 10). In applications that do not require voltage-positioning gain, the amplifier can be disabled by connecting the OAIN- pin directly to VCC. The disabled amplifier's output becomes a high impedance, guaranteeing that the unused amplifier does not corrupt the FB input signal. The logic threshold to disable the op amp is approximately VCC - 1V. Integrator Amplifier A feedback amplifier forces the DC average of the feedback voltage to equal the VID DAC setting. This transconductance amplifier integrates the feedback voltage and provides a fine adjustment to the regulation voltage (Figure 5), allowing accurate DC output voltage regulation regardless of the output ripple voltage. The feedback amplifier has the ability to shift the output voltage. The differential input voltage range is at least 80mV total, including DC offset and AC ripple. The integration time constant can be set easily with an external compensation capacitor at the CCV pin. Use a capacitor value of 47pF to 1000pF (47pF typ). Differential Remote Sense The multiphase Quick-PWM controllers include differential remote-sense inputs to eliminate the effects of voltage drops down the PC board traces and through the processor's power pins. The remote output sense (FBS) is accomplished by summing in the remote-sense voltage into the positive terminal of the voltage-positioning amplifier (Figure 10). The controller includes a dedicated input and internal amplifier for the remote ground sense. The GNDS amplifier adds an offset directly to the feedback voltage, adjusting the output voltage to counteract the voltage drop in the ground path. Together, the feedback sense resistor (R FBS ) and GNDS input sum the remote-sense voltages with the feedback signals that set the voltage-positioned output, enabling true differential remote sense of the processor voltage. Connect the feedback sense resistor (RFBS) and ground sense input (GNDS) directly to the processor's core supply remote-sense outputs as shown in the Standard Applications Circuit.
MAX1544
where VOS(IBAL) is the current balance offset specification in the Electrical Characteristics. The worst-case current mismatch occurs immediately after a load transient due to inductor value mismatches resulting in different di/dt for the two phases. The time it takes the current-balance loop to correct the transient imbalance depends on the mismatch between the inductor values and switching frequency.
Feedback Adjustment Amplifiers
Voltage-Positioning Amplifier The multiphase Quick-PWM controllers include an independent operational amplifier for adding gain to the voltage-positioning sense path. The voltage-positioning gain allows the use of low-value current-sense resistors in order to minimize power dissipation. This 3MHz gainbandwidth amplifier was designed with low offset voltage (70V typ) to meet the IMVP output accuracy requirements. The inverting (OAIN-) and noninverting (OAIN+) inputs are used to differentially sense the voltage across the voltage-positioning sense resistor. The op amp's output is internally connected to the regulator's feedback input (FB). The op amp should be configured as a noninverting, differential amplifier, as shown in Figure 10. The voltage-positioning slope is set by properly selecting the feedback resistor connected from FB to OAIN- (see the Setting Voltage Positioning section). For applications using a slave controller, additional differential input resistors (summing configuration) can be connected to the slave's voltage-positioning sense resistor. Summing together both the master and slave current-sense signals ensures that the voltage-positioning slope remains constant when the slave controller is disabled.
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Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies
Offset Amplifier The multiphase Quick-PWM controllers include a third amplifier used to add small offsets to the voltage-positioned load line. The offset amplifier is summed directly with the feedback voltage, making the offset gain independent of the DAC code. This amplifier has the ability to offset the output by 100mV. The offset is adjusted using resistive voltage-dividers at the OFS input. For inputs from 0 to 0.8V, the offset amplifier adds a negative offset to the output that is equal to 1/8 the voltage appearing at the selected OFS input (VOUT = VDAC - 0.125 x VOFS). For inputs from 1.2V to 2V, the offset amplifier adds a positive offset to the output that is equal to 1/8th the difference between the reference voltage and the voltage appearing at the selected OFS input (VOUT = VDAC + 0.125 x (VREF VOFS)). With this scheme, the controller supports both positive and negative offsets with a single input. The piecewise linear transfer function is shown in the Typical Operating Characteristics. The regions of the transfer function below zero, above 2V, and between 0.8V and 1.2V are undefined. OFS inputs are disallowed in these regions, and the respective effects on the output are not specified. The controller disables the offset amplifier during suspend mode (SUS = REF or high).
MAX1544
200 OUTPUT OFFSET VOLTAGE (mV) UNDEFINED REGION 100
0
-100
-200 0 0.5
0.8 1.0
1.2 1.5 2.0
OFS VOLTAGE (V)
Figure 6. Offset Voltage
reverse under light loads, providing fast, accurate negative output voltage transitions by quickly discharging the output capacitors. Forced-PWM operation comes at a cost: the no-load 5V bias supply current remains between 10mA to 60mA per phase, depending on the external MOSFETs and switching frequency. To maintain high efficiency under light-load conditions, the processor may switch the controller to a low-power pulse-skipping control scheme after entering suspend mode.
Forced-PWM Operation (Normal Mode)
During normal mode, when the CPU is actively running (SKIP = high, Table 7), the Quick-PWM controller operates with the low-noise forced-PWM control scheme. Forced-PWM operation disables the zero-crossing comparator, forcing the low-side gate-drive waveform to be constantly the complement of the high-side gatedrive waveform. This keeps the switching frequency fairly constant and allows the inductor current to
Low-Power Pulse Skipping
During pulse-skipping override mode (SKIP = REF or GND, Table 7), the multiphase Quick-PWM controllers use an automatic pulse-skipping control scheme. When SKIP is pulled low, the controller uses the automatic pulse-skipping control scheme, overriding forced-PWM operation, and blanks the upper VROK threshold.
Table 7. SKIP Settings*
SKIP CONNECTION High (3.3V or VCC) MODE Two-phase forced PWM OPERATION The controller operates with a constant switching frequency, providing low-noise forced-PWM operation. The controller disables the zero-crossing comparators, forcing the low-side gatedrive waveform to be constantly the complement of the high-side gate-drive waveform. The controller automatically switches over to PFM operation under light loads. The controller keeps both phases active and uses the automatic pulse-skipping control scheme, alternating between the primary and secondary phases with each cycle. The controller automatically switches over to PFM operation under light loads. Only the main phase is active. The secondary phase is disabled, DLS and DHS are pulled low, so LXS is a high impedance.
REF
Two-phase pulse skipping
GND
One-phase pulse skipping
*Settings for a dual 180 out-of-phase controller. 28 ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies
SKIP is a three-level logic input--GND, REF, or high. This input is intended to be driven by a dedicated open-drain output with the pullup resistor connected either to REF (or a resistive divider from VCC) or to a logic-level high-bias supply (3.3V or greater). When driven to GND, the multiphase Quick-PWM controller disables the secondary phase (DLS = PGND and DHS = LXS) and the primary phase uses the automatic pulse-skipping control scheme. When pulled up to REF, the controller keeps both phases active and uses the automatic pulse-skipping control scheme--alternating between the primary and secondary phases with each cycle. Automatic Pulse-Skipping Switchover In skip mode (SKIP = REF or GND), an inherent automatic switchover to PFM takes place at light loads (Figure 7). A comparator that truncates the low-side switch on-time at the inductor current's zero crossing affects this switchover. The zero-crossing comparator senses the inductor current across the current-sense resistors. Once VC_P - VC_N drops below the zero crossing comparator threshold (see the Electrical Characteristics), the comparator forces DL low (Figure 5). This mechanism causes the threshold between pulse-skipping PFM and nonskipping PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation. The PFM/PWM crossover occurs when the load current of each phase is equal to 1/2 the peak-topeak ripple current, which is a function of the inductor value (Figure 7). For a battery input range of 7V to 20V, this threshold is relatively constant, with only a minor dependence on the input voltage due to the typically low duty cycles. The total load current at the PFM/PWM crossover threshold (ILOAD(SKIP)) is approximately: K V - V V ILOAD(SKIP) = TOTAL OUT IN OUT L VIN where TOTAL is the number of active phases, and K is the on-time scale factor (Table 6). The switching waveforms may appear noisy and asynchronous when light loading activates pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Varying the inductor value makes trade-offs between PFM noise and light-load efficiency. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response, especially at low input voltage levels.
MAX1544
i t INDUCTOR CURRENT
=
VBATT - VOUT L
IPEAK
ILOAD = IPEAK/2
0
ON-TIME
TIME
Figure 7. Pulse-Skipping/Discontinuous Crossover Point
IPEAK
ILOAD INDUCTOR CURRENT
ILIMIT
ILIMIT(VALLEY) = ILOAD(MAX)
(
2 - LIR 2
)
0 TIME
Figure 8. "Valley" Current-Limit Threshold Point
Current-Limit Circuit
The current-limit circuit employs a unique "valley" current-sensing algorithm that uses current-sense resistors between the current-sense inputs (C_P to C_N) as the current-sensing elements. If the current-sense signal of the selected phase is above the current-limit threshold, the PWM controller does not initiate a new cycle (Figure 8) until the inductor current of the selected phase drops below the valley current-limit threshold. When either phase trips the current limit, both phases are effectively current limited since the interleaved controller does not initiate a cycle with either phase.
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Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies MAX1544
Since only the valley current is actively limited, the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the current-sense resistance, inductor value, and battery voltage. When combined with the undervoltage protection circuit, this current-limit method is effective in almost every circumstance. There is also a negative current limit that prevents excessive reverse inductor currents when V OUT is sinking current. The negative current-limit threshold is set to approximately 120% of the positive current limit, and therefore tracks the positive current limit when ILIM is adjusted. When a phase drops below the negative current limit, the controller immediately activates an ontime pulse--DL turns off, and DH turns on--allowing the inductor current to remain above the negative current threshold. The current-limit threshold is adjusted with an external resistive voltage-divider at ILIM. The current-limit threshold voltage adjustment range is from 10mV to 75mV. In the adjustable mode, the current-limit threshold voltage is precisely 1/20 the voltage seen at ILIM. The threshold defaults to 30mV when ILIM is connected to VCC. The logic threshold for switchover to the 30mV default value is approximately VCC - 1V. Carefully observe the PC board layout guidelines to ensure that noise and DC errors do not corrupt the current-sense signals seen by the current-sense inputs (C_P, C_N). pling from the drain to the gate of the low-side MOSFETs when LX switches from ground to V IN . Applications with high input voltages and long, inductive DL traces may require additional gate-to-source capacitance to ensure fast-rising LX edges do not pull up the low-side MOSFET's gate voltage, causing shootthrough currents. The capacitive coupling between LX and DL created by the MOSFET's gate-to-drain capacitance (C RSS ), gate-to-source capacitance (C ISS C RSS ), and additional board parasitics should not exceed the minimum threshold voltage: C VGS(TH) < VIN RSS CISS Lot-to-lot variation of the threshold voltage can cause problems in marginal designs. Typically, adding 4700pF between DL and power ground (C NL in Figure 9), close to the low-side MOSFETs, greatly reduces coupling. Do not exceed 22nF of total gate capacitance to prevent excessive turn-off delays. Alternatively, shoot-through currents may be caused by a combination of fast high-side MOSFETs and slow lowside MOSFETs. If the turn-off delay time of the low-side MOSFET is too long, the high-side MOSFETs can turn on before the low-side MOSFETs have actually turned off. Adding a resistor less than 5 in series with BST slows down the high-side MOSFET turn-on time, eliminating the shoot-through currents without degrading the turn-off time (RBST in Figure 9). Slowing down the high-side MOSFET also reduces the LX node rise time, thereby reducing EMI and high-frequency coupling responsible for switching noise.
CBYP VDD DBST BST (RBST)* INPUT (VIN) NH L
MOSFET Gate Drivers (DH, DL)
The DH and DL drivers are optimized for driving moderately sized, high-side and larger, low-side power MOSFETs. This is consistent with the low-duty factor seen in the notebook CPU environment, where a large VIN - VOUT differential exists. An adaptive dead-time circuit monitors the DL output and prevents the highside FET from turning on until DL is fully off. There must be a low-resistance, low-inductance path from the DL driver to the MOSFET gate in order for the adaptive dead-time circuit to work properly. Otherwise, the sense circuitry in the Quick-PWM controller interprets the MOSFET gate as "off" while there is actually charge still left on the gate. Use very short, wide traces (50 mils to 100 mils wide if the MOSFET is 1in from the device). The dead time at the other edge (DH turning off) is determined by a fixed 35ns internal delay. The internal pulldown transistor that drives DL low is robust, with a 0.4 (typ) on-resistance. This helps prevent DL from being pulled up due to capacitive cou30
CBST DH
LX VDD DL (CNL)* PGND NL
(RBST)* OPTIONAL--THE RESISTOR LOWERS EMI BY DECREASING THE SWITCHING NODE RISE TIME. (CNL)* OPTIONAL--THE CAPACITOR REDUCES LX TO DL CAPACITIVE COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.
Figure 9. Optional Gate-Driver Circuitry ______________________________________________________________________________________
Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies
Power-On Reset
Power-on reset (POR) occurs when VCC rises above approximately 2V, resetting the fault latch, activating boot mode, and preparing the PWM for operation. VCC undervoltage lockout (UVLO) circuitry inhibits switching, and forces the DL gate driver high (to enforce output overvoltage protection). When V CC rises above 4.25V, the DAC inputs are sampled and the output voltage begins to slew to the target voltage. For automatic startup, the battery voltage should be present before V CC . If the Quick-PWM controller attempts to bring the output into regulation without the battery voltage present, the fault latch trips. Toggle the SHDN pin to reset the fault latch. ponents. Modern notebook CPUs generally exhibit ILOAD = ILOAD(MAX) x 80%. For multiphase systems, each phase supports a fraction of the load, depending on the current balancing. When properly balanced, the load current is evenly distributed among each phase: ILOAD(PHASE) = ILOAD TOTAL
MAX1544
*
Input Undervoltage Lockout
During startup, the VCC UVLO circuitry forces the DL gate driver high and the DH gate driver low, inhibiting switching until an adequate supply voltage is reached. Once VCC rises above 4.25V, valid transitions detected at the trigger input initiate a corresponding on-time pulse (see the On-Time One-Shot (TON) section). If the V CC voltage drops below 4.25V, it is assumed that there is not enough supply voltage to make valid decisions. To protect the output from overvoltage faults, the controller activates the shutdown sequence.
*
Multiphase Quick-PWM Design Procedure
Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: * Input voltage range: The maximum value (VIN(MAX)) must accommodate the worst-case high AC adapter voltage. The minimum value (VIN(MIN)) must account for the lowest input voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency. * Maximum load current: There are two values to consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and filtering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing com-
where TOTAL is the total number of active phases. Switching frequency: This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage due to MOSFET switching losses that are proportional to frequency and VIN2. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical. Inductor operating point: This choice provides trade-offs between size vs. efficiency and transient response vs. output noise. Low-inductor values provide better transient response and smaller physical size, but also result in lower efficiency and higher output noise due to increased ripple current. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The optimum operating point is usually found between 20% and 50% ripple current.
Inductor Selection
The switching frequency and operating point (% ripple current or LIR) determine the inductor value as follows: VIN - VOUT VOUT L = TOTAL fSWILOAD(MAX)LIR VIN where TOTAL is the total number of phases. Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK): I LIR IPEAK = LOAD(MAX) 1 + TOTAL 2
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Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies MAX1544
Transient Response
The inductor ripple current impacts transient-response performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The amount of output sag is also a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time. For a dual-phase controller, the worst-case output sag voltage can be determined by:
V K L(ILOAD(MAX))2 OUT + tOFF(MIN) VIN
Output Capacitor Selection
The output filter capacitor must have low enough effective series resistance (ESR) to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements. In CPU VCORE converters and other applications where the output is subject to large-load transients, the output capacitor's size typically depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance: RESR VSTEP ILOAD(MAX)
VSAG =
(VIN - 2VOUT)K 2COUTVOUT - 2tOFF(MIN) VIN VOUTK I + LOAD(MAX) + tOFF(MIN) 2COUT VIN
where t OFF(MIN) is the minimum off-time (see the Electrical Characteristics) and K is from Table 6. The amount of overshoot due to stored inductor energy can be calculated as: VSOAR (ILOAD(MAX))2 L 2 TOTAL COUT VOUT
In non-CPU applications, the output capacitor's size often depends on how much ESR is needed to maintain an acceptable level of output ripple voltage. The output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capacitor's ESR. When operating multiphase systems out-ofphase, the peak inductor currents of each phase are staggered, resulting in lower output ripple voltage by reducing the total inductor ripple current. For 3- or 4-phase operation, the maximum ESR to meet ripple requirements is:
RESR VRIPPLEL (2VIN - TOTAL VOUT )t ON - TOTALVOUT t TRIG
where TOTAL is the total number of active phases.
Setting the Current Limit
The minimum current-limit threshold must be high enough to support the maximum load current when the current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus half the ripple current; therefore: I LIR ILIMIT(LOW) > LOAD(MAX) 1 - TOTAL 2 where TOTAL is the total number of active phases, and ILIMIT(LOW) equals the minimum current-limit threshold voltage divided by the current-sense resistor (RSENSE). For the 30mV default setting, the minimum current-limit threshold is 28mV. Connect ILIM to VCC for the default current-limit threshold (see the Electrical Characteristics). In adjustable mode, the current-limit threshold is precisely 1/20 the voltage seen at ILIM. For an adjustable threshold, connect a resistive divider from REF to GND with ILIM connected to the center tap. When adjusting the current limit, use 1% tolerance resistors with approximately 10A of divider current to prevent a significant increase of errors in the current-limit tolerance.
32
where TOTAL is the total number of active phases, tON is the calculated on-time per phase, and tTRIG is the trigger delay between the master's DH rising edge and the slave's DH rising edge. The trigger delay must be less than 1/(fSW x TOTAL) for stable operation. The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of polymer types). When using low-capacity ceramic filter capacitors, capacitor size is usually determined by the capacity needed to prevent V SAG and V SOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the VSAG and VSOAR equations in the Transient Response section).
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Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies
Output Capacitor Stability Considerations
For Quick-PWM controllers, stability is determined by the value of the ESR zero relative to the switching frequency. The boundary of instability is given by the following equation: fESR where: fESR = and: REFF = RESR + AVPSRSENSE + RPCB where COUT is the total output capacitance, RESR is the total equivalent-series resistance, R SENSE is the current-sense resistance, AVPS is the voltage-positioning gain, and R PCB is the parasitic board resistance between the output capacitors and sense resistors. For a standard 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below 50kHz. Tantalum, Sanyo POSCAP, and Panasonic SP capacitors in widespread use at the time of publication have typical ESR-zero frequencies below 50kHz. For example, the ESR needed to support a 30mVP-P ripple in a 40A design is 30mV/(40A x 0.3) = 2.5m. Four 330F/2.5V Panasonic SP (type XR) capacitors in parallel provide 2.5m (max) ESR. Their typical combined ESR results in a zero at 40kHz. Ceramic capacitors have a high ESR zero frequency, but applications with significant voltage positioning can take advantage of their size and low ESR. Do not put high-value ceramic capacitors directly across the output without verifying that the circuit contains enough voltage positioning and series PC board resistance to ensure stability. When only using ceramic output capacitors, output overshoot (VSOAR) typically determines the minimum output capacitance requirement. Their relatively low capacitance value can cause output overshoot when stepping from full-load to no-load conditions, unless a small inductor value is used (high switching frequency) to minimize the energy transferred from inductor to capacitor during load-step recovery. The efficiency penalty for operating at 550kHz is about 5% when compared to the 300kHz circuit, primarily due to the high-side MOSFET switching losses. 1 2REFF COUT fSW Unstable operation manifests itself in two related but distinctly different ways: double-pulsing and feedback loop instability. Double-pulsing occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output voltage signal. This "fools" the error comparator into triggering a new cycle immediately after the minimum off-time period has expired. Double-pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability due to insufficient ESR. Loop instability can result in oscillations at the output after line or load steps. Such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for overshoot and ringing. It can help to simultaneously monitor the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial step-response under/overshoot.
MAX1544
Input Capacitor Selection
The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents. The multiphase Quick-PWM controllers operate out-ofphase, while the Quick-PWM slave controllers provide selectable out-of-phase or in-phase on-time triggering. Out-of-phase operation reduces the RMS input current by dividing the input current between several staggered stages. For duty cycles less than 100%/OUTPH per phase, the IRMS requirements may be determined by the following equation:
ILOAD IRMS = OUTPH VIN OUTPH VOUT (VIN - OUTPH VOUT)
where OUTPH is the total number of out-of-phase switching regulators. The worst-case RMS current requirement occurs when operating with VIN = 2OUTPHVOUT. At this point, the above equation simplifies to IRMS = 0.5 x ILOAD/OUTPH. For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CONTM) are preferred due to their resistance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. If the Quick-PWM controller is operated as the second stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. In either configuration, choose an input capacitor that exhibits less than 10C temperature rise at the RMS input current for optimal circuit longevity.
OS-CON is a trademark of Sanyo. 33
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Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies MAX1544
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (>20V) AC adapters. Low-current applications usually require less attention. The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both VIN(MIN) and VIN(MAX). Calculate both of these sums. Ideally, the losses at VIN(MIN) should be roughly equal to losses at VIN(MAX), with lower losses in between. If the losses at VIN(MIN) are significantly higher than the losses at VIN(MAX), consider increasing the size of NH (reducing RDS(ON) but with higher CGATE). Conversely, if the losses at VIN(MAX) are significantly higher than the losses at VIN(MIN), consider reducing the size of NH (increasing RDS(ON) to lower CGATE). If VIN does not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses. Choose a low-side MOSFET that has the lowest possible on-resistance (R DS(ON)), comes in a moderatesized package (i.e., one or two SO-8s, DPAK, or D2PAK), and is reasonably priced. Ensure that the DL gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic gate-to-drain capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems can occur (see the MOSFET Gate Driver section). characteristics. The following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH:
f I C PD (NH SWITCHING) = (VIN(MAX))2 RSS SW LOAD IGATE TOTAL
where CRSS is the reverse transfer capacitance of NH and IGATE is the peak gate-drive source/sink current (1A typ). Switching losses in the high-side MOSFET can become an insidious heat problem when maximum AC adapter voltages are applied due to the squared term in the C x V IN2 x f SW switching-loss equation. If the high-side MOSFET chosen for adequate RDS(ON) at low battery voltages becomes extraordinarily hot when biased from V IN(MAX) , consider choosing another MOSFET with lower parasitic capacitance. For the low-side MOSFET (NL), the worst-case power dissipation always occurs at maximum input voltage:
VOUT ILOAD 2 PD (NL RESISTIVE) = 1 - RDS(ON) VIN(MAX) TOTAL
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at the minimum input voltage: 2 RDS(ON) where TOTAL is the total number of phases. Generally, a small high-side MOSFET is desired to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package power dissipation often limits how small the MOSFET can be. Again, the optimum occurs when the switching losses equal the conduction (RDS(ON)) losses. Highside switching losses do not usually become an issue until the input is greater than approximately 15V. Calculating the power dissipation in high-side MOSFET (NH) due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PC board layout
34
The worst-case for MOSFET power dissipation occurs under heavy overloads that are greater than ILOAD(MAX) but are not quite high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, you can "overdesign" the circuit to tolerate:
I ILOAD = TOTAL IVALLEY(MAX) + INDUCTOR 2 LIR I = TOTAL IVALLEY(MAX) + LOAD(MAX) 2
V I PD (NH RESISTIVE) = OUT LOAD VIN TOTAL
where I VALLEY(MAX) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. The MOSFETs must have a good-size heatsink to handle the overload power dissipation. Choose a Schottky diode (DL) with a forward voltage low enough to prevent the low-side MOSFET body diode from turning on during the dead time. As a general rule, select a diode with a DC current rating equal to 1/3 of the load current-per-phase. This diode is optional and can be removed if efficiency is not critical.
Boost Capacitors
The boost capacitors (CBST) must be selected large enough to handle the gate charging requirements of the high-side MOSFETs. Typically, 0.1F ceramic capacitors work well for low-power applications driving
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Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies
medium-sized MOSFETs. However, high-current applications driving large, high-side, MOSFETs require boost capacitors larger than 0.1F. For these applications, select the boost capacitors to avoid discharging the capacitor more than 200mV while charging the high-side MOSFET's gates: CBST = N x QGATE 200mV
Setting Voltage Positioning
Voltage positioning dynamically lowers the output voltage in response to the load current, reducing the processor's power dissipation. When the output is loaded, an operational amplifier (Figure 5) increases the signal fed back to the Quick-PWM controller's feedback input. The adjustable amplification allows the use of standard, current-sense resistor values, and significantly reduces the power dissipated since smaller current-sense resistors can be used. The load transient response of this control loop is extremely fast, yet well controlled, so the amount of voltage change can be accurately confined within the limits stipulated in the microprocessor power-supply guidelines. The voltage-positioned circuit determines the load current from the voltage across the current-sense resistors (RSENSE = RCM = RCS) connected between the inductors and output capacitors, as shown in Figure 10. The voltage drop can be determined by the following equation: VVPS = AVPSILOADRSENSE SUM RF AVPS = TOTAL RB where SUM is the number of phases summed together for voltage-positioning feedback, and TOTAL is the total number of active phases. When the slave controller is disabled, the current-sense summation maintains the proper voltage-positioned slope. Select the positive input summing resistors so RFBS = RF and RA = RB.
MAX1544
where N is the number of high-side MOSFETs used for one regulator, and QGATE is the gate charge specified in the MOSFET's data sheet. For example, assume two IRF7811W N-channel MOSFETs are used on the high side. According to the manufacturer's data sheet, a single IRF7811W has a maximum gate charge of 24nC (VGS = 5V). Using the above equation, the required boost capacitance would be: CBST = 2 x 24nC = 0.24F 200mV
Selecting the closest standard value, this example requires a 0.22F ceramic capacitor.
Current-Balance Compensation (CCI)
The current-balance compensation capacitor (CCCI) integrates the difference between the main and secondary current-sense voltages. The internal compensation resistor (RCCI = 20k) improves transient response by increasing the phase margin. This allows the dynamics of the current balance loop to be optimized. Excessively large capacitor values increase the integration time constant, resulting in larger current differences between the phases during transients. Excessively small capacitor values allow the current loop to respond cycle-by-cycle but can result in small DC current variations between the phases. Likewise, excessively large resistor values can also cause DC current variations between the phases. Small resistor values reduce the phase margin, resulting in marginal stability in the current-balance loop. For most applications, a 470pF capacitor from CCI to the switching regulator's output works well. Connecting the compensation network to the output (VOUT) allows the controller to feed forward the output voltage signal, especially during transients. To reduce noise pickup in applications that have a widely distributed layout, it is sometimes helpful to connect the compensation network to the quiet analog ground rather than VOUT.
Minimum Input Voltage Requirements and Dropout Performance
The nonadjustable minimum off-time one-shot and the number of phases restrict the output voltage adjustable range for continuous-conduction operation. For best dropout performance, use the slower (200kHz) on-time settings. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. Manufacturing tolerances and internal propagation delays introduce an error to the TON K factor. This error is greater at higher frequencies (Table 6). Also, keep in mind that transient response performance of buck regulators operated too close to dropout is poor, and bulk output capacitance must often be added (see the VSAG equation in the Design Procedure section). The absolute point of dropout is when the inductor current ramps down during the minimum off-time (IDOWN) as much as it ramps up during the on-time (IUP). The ratio h = IUP/IDOWN is an indicator of the ability to
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35
Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies MAX1544
CMN CMP MAIN PHASE MAX1544 RA OAIN+ RFBS
ERROR COMPARATOR
L1
RSENSE
RB PC BOARD TRACE RESISTANCE CPU SENSE POINT PC BOARD TRACE RESISTANCE
OAINFB RF RA SECOND PHASE CSP CSN L2 RB RSENSE
Figure 10. Voltage-Positioning Gain
slew the inductor current higher in response to increased load, and must always be greater than 1. As h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle and V SAG greatly increases unless additional output capacitance is used. A reasonable minimum value for h is 1.5, but adjusting this up or down allows tradeoffs between VSAG, output capacitance, and minimum operating voltage. For a given value of h, the minimum operating voltage can be calculated as: V -V FB VPS + VDROP1 VIN(MIN) = OUTPH h x tOFF(MIN) 1 - OUTPH K + VDROP2 - VDROP1 + VVPS where OUTPH is the total number of out-of-phase switching regulators, VVPS is the voltage-positioning droop, VDROP1 and VDROP2 are the parasitic voltage drops in the discharge and charge paths (see the On-Time OneShot (TON) section), tOFF(MIN) is from the Electrical Characteristics, and K is taken from Table 6. The absolute minimum input voltage is calculated with h = 1. If the calculated VIN(MIN) is greater than the required minimum input voltage, then reduce the operating frequency or add output capacitance to obtain an acceptable VSAG. If operation near dropout is anticipated, calculate VSAG to be sure of adequate transient response.
36
Dropout design example: VFB = 1.4V KMIN = 3s for fSW = 300kHz tOFF(MIN) = 400ns VVPS = 3mV/A x 30A = 90mV VDROP1 = VDROP2 = 150mV (30A load) h = 1.5 and OUTPH = 2 1.4V - 90mV + 150mV VIN(MIN) = 2 x 1 - 2 x (0.4s x 1.5 / 3.0s + 150mV - 150mV + 90mV = 4.96V Calculating again with h = 1 gives the absolute limit of dropout: 1.4V - 90mV + 150mV VIN(MIN) = 2 x 1 - 2 x (0.4s x 1.0 / 3.0s + 150mV - 150mV + 90mV = 4.07V Therefore, VIN must be greater than 4.1V, even with very large output capacitance, and a practical input voltage with reasonable output capacitance would be 5V.
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Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies
Applications Information
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention (Figure 11). If possible, mount all of the power components on the topside of the board with their ground terminals flush against one another. Follow these guidelines for good PC board layout: 1) Keep the high-current paths short, especially at the ground terminals. This is essential for stable, jitter-free operation. 2) Connect all analog grounds to a separate solid copper plane, which connects to the GND pin of the Quick-PWM controller. This includes the VCC bypass capacitor, REF and GNDS bypass capacitors, compensation (CC_) components, and the resistive dividers connected to ILIM and OFS. 3) Each slave controller should also have a separate analog ground. Return the appropriate noise-sensitive slave components to this plane. Since the reference in the master is sometimes connected to the slave, it may be necessary to couple the analog ground in the master to the analog ground in the slave to prevent ground offsets. A low-value (10) resistor is sufficient to link the two grounds. 4) Keep the power traces and load connections short. This is essential for high efficiency. The use of thick copper PC boards (2oz vs. 1oz) can enhance fullload efficiency by 1% or more. Correctly routing PC board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single m of excess trace resistance causes a measurable efficiency penalty. 5) Keep the high-current, gate-driver traces (DL, DH, LX, and BST) short and wide to minimize trace resistance and inductance. This is essential for high-power MOSFETs that require low-impedance gate drivers to avoid shoot-through currents. 6) C_P, C_N, OAIN+, and OAIN- connections for current limiting and voltage positioning must be made using Kelvin-sense connections to guarantee the current-sense accuracy. 7) When trade-offs in trace lengths must be made, it is preferable to allow the inductor-charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the 8) inductor and the low-side MOSFET or between the inductor and the output filter capacitor. Route high-speed switching nodes away from sensitive analog areas (REF, CCV, CCI, FB, C_P, C_N, etc). Make all pin-strap control input connections (SHDN, ILIM, SKIP, SUS, S_, TON) to analog ground or VCC rather than power ground or VDD.
MAX1544
Layout Procedure
Place the power components first, with ground terminals adjacent (low-side MOSFET source, CIN, COUT, and D1 anode). If possible, make all these connections on the top layer with wide, copper-filled areas. 1) Mount the controller IC adjacent to the low-side MOSFET. The DL gate traces must be short and wide (50 mils to 100 mils wide if the MOSFET is 1in from the controller IC). Group the gate-drive components (BST diodes and capacitors, VDD bypass capacitor) together near the controller IC. Make the DC-to-DC controller ground connections as shown in the Standard Application Circuits. This diagram can be viewed as having four separate ground planes: input/output ground, where all the high-power components go; the power ground plane, where the PGND pin and V DD bypass capacitor go; the master's analog ground plane, where sensitive analog components, the master's GND pin, and VCC bypass capacitor go; and the slave's analog ground plane, where the slave's GND pin and VCC bypass capacitor go. The master's GND plane must meet the PGND plane only at a single point directly beneath the IC. Similarly, the slave's GND plane must meet the PGND plane only at a single point directly beneath the IC. The respective master and slave ground planes should connect to the high-power output ground with a short metal trace from PGND to the source of the low-side MOSFET (the middle of the star ground). This point must also be very close to the output capacitor ground terminal. Connect the output power planes (V CORE and system ground planes) directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-to-DC converter circuit as close to the CPU as is practical.
2)
3)
4)
Chip Information
TRANSISTOR COUNT: 11,015 PROCESS: BiCMOS
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37
Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies MAX1544
KELVIN SENSE VIAS UNDER THE SENSE RESISTOR (REFER TO EVALUATION KIT) MAIN PHASE
CPU
SECONDARY PHASE
RSENSE COUT COUT COUT
OUTPUT COUT COUT COUT
RSENSE
INDUCTOR
INDUCTOR
POWER GROUND
CIN
CIN
CIN
CIN
CIN
INPUT
PLACE CONTROLLER ON BACK SIDE WHEN POSSIBLE, USING THE GROUND PLANE TO SHIELD THE IC FROM EMI
VIAS TO POWER GROUND
POWER GROUND (2ND LAYER)
CONNECT THE EXPOSED PAD TO ANALOG GND
CIN CONNECT GND AND PGND TO THE CONTROLLER AT ONE POINT ONLY AS SHOWN
VIA TO ANALOG GROUND
POWER GROUND (2ND LAYER)
Figure 11. PC Board Layout Example
38
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Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies MAX1544
C1 2.2F VDD VCC U1 MAX1544 POWER GOOD VROK D0 D1 D2 D3 D4 S0 S1 SHDN RTIME 64.9k TIME CCCV 47pF CCV OUTPUT CREF 0.22F REF (300kHz) TON REF R8 R9 22.6k 100k 1% 1% ILIM REF CREF 0.22F R6 20k 1% OFS R7 182k 1% OVP SKIP GND POWER GROUND ANALOG GROUND *LOWER INPUT VOLTAGES REQUIRE ADDITIONAL INPUT CAPACITANCE. GNDS FB CCCI 470pF CCI CSP CSN BSTS CBST2 0.22F DHS LXS DLS VCC (OVP ENABLED) PWM SKIP COUT NL2 NH2 L2 RSENSE2 1.0m R1 1.65k 1% R4 1k 1% GND CMN CMP OAIN+ OAINV+ BSTM CBST1 0.22F DHM LXM DLM SUSPEND INPUTS (FOUR-LEVEL LOGIC) ON OFF PGND R2 1k 1% NL1 R3 1k 1% R6 1.65k 1% NH1 L1 RSENSE1 1.0m COUT BST DIODES INPUT* 7V TO 24V 5V BIAS SUPPLY
R11 100k
R10 10 C2 1F
CIN
DAC INPUTS
R5 1k 1%
CIN
Figure 12a. Standard AMD Desktop 70A Application Circuit (1st and 2nd Phases--MAX1544 Master)
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39
Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies MAX1544
5V BIAS SUPPLY
R12 10 C6 0.22F D1 1N4148 OUTPUT CCOMP1 RCOMP1 270pF 20k R17 200k ILIM C9 100pF PGND R18 49.9k GND CS+ COMP U2 MAX1980 VCC POL VDD DBST3 V+ BST DH LX DL
C5 1F
CIN
INPUT* 7V TO 24V
CBST3 0.22F
NH3 L3
RSENSE3 1.0m
OUTPUT COUT
NL3
REF (MASTER)
R13 100 C7 1000pF R14 100 R15 100
FLOAT (300kHz)
TON LIMIT DD TRIG
CS-
CM+ C8 1000pF R16 100
SKIP (MASTER)
DLM (MASTER)
CM-
CONNECT TO MAX1544 (SEE FIGURE 12a) POWER GROUND ANALOG GROUND (MASTER)
CONNECT TO MAX1544 (SEE FIGURE 12a) *LOWER INPUT VOLTAGES REQUIRE ADDITIONAL INPUT CAPACITANCE.
Figure 12b. Standard AMD Desktop 70A Application Circuit (3rd Phase--MAX1980 Slave)
40
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CMN
CMP
Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies MAX1544
5V BIAS SUPPLY
R19 10 C11 0.22F D2 1N4148 OUTPUT CCOMP2 RCOMP2 270pF 20k R24 200k ILIM C14 100pF PGND R25 49.9k GND CS+ COMP U3 MAX1980 VCC POL VDD DBST4 V+ BST DH LX DL
C10 1F
CIN
INPUT* 7V TO 24V
CBST4 0.22F
NH4 L4
RSENSE4 1.0m
OUTPUT COUT
NL4
REF (MASTER)
R20 100 C12 1000pF R21 100 R22 100
FLOAT (300kHz)
TON LIMIT DD TRIG
CS-
CM+ C13 1000pF R23 100
SKIP (MASTER)
DLS (MASTER)
CM-
CONNECT TO MAX1544 (SEE FIGURE 12a) POWER GROUND ANALOG GROUND (MASTER)
CONNECT TO MAX1544 (SEE FIGURE 12a) *LOWER INPUT VOLTAGES REQUIRE ADDITIONAL INPUT CAPACITANCE.
Figure 12c. Standard AMD Desktop 70A Application Circuit (4th Phase--MAX1980 Slave)
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CSN
CSP
41
Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies MAX1544
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QFN THIN 6x6x0.8.EPS
E2 L e
D2 D D/2 k
C L
b D2/2
E/2 E2/2 E (NE-1) X e
C L
k
e (ND-1) X e
L
C L
C L
L
e
A1
A2
A
PACKAGE OUTLINE 36,40L QFN THIN, 6x6x0.8 mm
21-0141
C
1 2
COMMON DIMENSIONS
PKG. CODES T3666-1 T4066-1
EXPOSED PAD VARIATIONS
D2 E2 MIN. NOM. MAX. MIN. NOM. MAX. 3.60 4.00 3.70 4.10 3.80 4.20 3.60 4.00 3.70 4.10 3.80 4.20
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220. 10. WARPAGE SHALL NOT EXCEED 0.10 mm.
PACKAGE OUTLINE 36, 40L QFN THIN, 6x6x0.8 mm
21-0141
C
2 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
42 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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